/*******************************************************************************
* File Name: cydevice_trm.h
* 
* PSoC Creator  4.1 Update 1
*
* Description:
* This file provides all of the address values for the entire PSoC device.
* This file is automatically generated by PSoC Creator.
*
********************************************************************************
* Copyright (c) 2007-2017 Cypress Semiconductor.  All rights reserved.
* You may use this file only in accordance with the license, terms, conditions, 
* disclaimers, and limitations in the end user license agreement accompanying 
* the software package with which this file was provided.
********************************************************************************/

#if !defined(CYDEVICE_TRM_H)
#define CYDEVICE_TRM_H
#define CYDEV_FLASH_BASE 0x00000000u
#define CYDEV_FLASH_SIZE 0x00008000u
#define CYREG_FLASH_DATA_MBASE 0x00000000u
#define CYREG_FLASH_DATA_MSIZE 0x00008000u
#define CYDEV_SFLASH_BASE 0x0ffff000u
#define CYDEV_SFLASH_SIZE 0x00000200u
#define CYREG_SFLASH_PROT_ROW00 0x0ffff000u
#define CYFLD_SFLASH_DATA8__OFFSET 0x00000000u
#define CYFLD_SFLASH_DATA8__SIZE 0x00000008u
#define CYREG_SFLASH_PROT_ROW01 0x0ffff001u
#define CYREG_SFLASH_PROT_ROW02 0x0ffff002u
#define CYREG_SFLASH_PROT_ROW03 0x0ffff003u
#define CYREG_SFLASH_PROT_ROW04 0x0ffff004u
#define CYREG_SFLASH_PROT_ROW05 0x0ffff005u
#define CYREG_SFLASH_PROT_ROW06 0x0ffff006u
#define CYREG_SFLASH_PROT_ROW07 0x0ffff007u
#define CYREG_SFLASH_PROT_ROW08 0x0ffff008u
#define CYREG_SFLASH_PROT_ROW09 0x0ffff009u
#define CYREG_SFLASH_PROT_ROW10 0x0ffff00au
#define CYREG_SFLASH_PROT_ROW11 0x0ffff00bu
#define CYREG_SFLASH_PROT_ROW12 0x0ffff00cu
#define CYREG_SFLASH_PROT_ROW13 0x0ffff00du
#define CYREG_SFLASH_PROT_ROW14 0x0ffff00eu
#define CYREG_SFLASH_PROT_ROW15 0x0ffff00fu
#define CYREG_SFLASH_PROT_ROW16 0x0ffff010u
#define CYREG_SFLASH_PROT_ROW17 0x0ffff011u
#define CYREG_SFLASH_PROT_ROW18 0x0ffff012u
#define CYREG_SFLASH_PROT_ROW19 0x0ffff013u
#define CYREG_SFLASH_PROT_ROW20 0x0ffff014u
#define CYREG_SFLASH_PROT_ROW21 0x0ffff015u
#define CYREG_SFLASH_PROT_ROW22 0x0ffff016u
#define CYREG_SFLASH_PROT_ROW23 0x0ffff017u
#define CYREG_SFLASH_PROT_ROW24 0x0ffff018u
#define CYREG_SFLASH_PROT_ROW25 0x0ffff019u
#define CYREG_SFLASH_PROT_ROW26 0x0ffff01au
#define CYREG_SFLASH_PROT_ROW27 0x0ffff01bu
#define CYREG_SFLASH_PROT_ROW28 0x0ffff01cu
#define CYREG_SFLASH_PROT_ROW29 0x0ffff01du
#define CYREG_SFLASH_PROT_ROW30 0x0ffff01eu
#define CYREG_SFLASH_PROT_ROW31 0x0ffff01fu
#define CYREG_SFLASH_PROT_ROW32 0x0ffff020u
#define CYREG_SFLASH_PROT_ROW33 0x0ffff021u
#define CYREG_SFLASH_PROT_ROW34 0x0ffff022u
#define CYREG_SFLASH_PROT_ROW35 0x0ffff023u
#define CYREG_SFLASH_PROT_ROW36 0x0ffff024u
#define CYREG_SFLASH_PROT_ROW37 0x0ffff025u
#define CYREG_SFLASH_PROT_ROW38 0x0ffff026u
#define CYREG_SFLASH_PROT_ROW39 0x0ffff027u
#define CYREG_SFLASH_PROT_ROW40 0x0ffff028u
#define CYREG_SFLASH_PROT_ROW41 0x0ffff029u
#define CYREG_SFLASH_PROT_ROW42 0x0ffff02au
#define CYREG_SFLASH_PROT_ROW43 0x0ffff02bu
#define CYREG_SFLASH_PROT_ROW44 0x0ffff02cu
#define CYREG_SFLASH_PROT_ROW45 0x0ffff02du
#define CYREG_SFLASH_PROT_ROW46 0x0ffff02eu
#define CYREG_SFLASH_PROT_ROW47 0x0ffff02fu
#define CYREG_SFLASH_PROT_ROW48 0x0ffff030u
#define CYREG_SFLASH_PROT_ROW49 0x0ffff031u
#define CYREG_SFLASH_PROT_ROW50 0x0ffff032u
#define CYREG_SFLASH_PROT_ROW51 0x0ffff033u
#define CYREG_SFLASH_PROT_ROW52 0x0ffff034u
#define CYREG_SFLASH_PROT_ROW53 0x0ffff035u
#define CYREG_SFLASH_PROT_ROW54 0x0ffff036u
#define CYREG_SFLASH_PROT_ROW55 0x0ffff037u
#define CYREG_SFLASH_PROT_ROW56 0x0ffff038u
#define CYREG_SFLASH_PROT_ROW57 0x0ffff039u
#define CYREG_SFLASH_PROT_ROW58 0x0ffff03au
#define CYREG_SFLASH_PROT_ROW59 0x0ffff03bu
#define CYREG_SFLASH_PROT_ROW60 0x0ffff03cu
#define CYREG_SFLASH_PROT_ROW61 0x0ffff03du
#define CYREG_SFLASH_PROT_ROW62 0x0ffff03eu
#define CYREG_SFLASH_PROT_ROW63 0x0ffff03fu
#define CYREG_SFLASH_PROT_PROTECTION 0x0ffff07fu
#define CYFLD_SFLASH_PROT_LEVEL__OFFSET 0x00000000u
#define CYFLD_SFLASH_PROT_LEVEL__SIZE 0x00000002u
#define CYVAL_SFLASH_PROT_LEVEL_VIRGIN 0x00000001u
#define CYVAL_SFLASH_PROT_LEVEL_OPEN 0x00000000u
#define CYVAL_SFLASH_PROT_LEVEL_PROTECTED 0x00000002u
#define CYVAL_SFLASH_PROT_LEVEL_KILL 0x00000003u
#define CYREG_SFLASH_AV_PAIRS_8B000 0x0ffff080u
#define CYREG_SFLASH_AV_PAIRS_8B001 0x0ffff081u
#define CYREG_SFLASH_AV_PAIRS_8B002 0x0ffff082u
#define CYREG_SFLASH_AV_PAIRS_8B003 0x0ffff083u
#define CYREG_SFLASH_AV_PAIRS_8B004 0x0ffff084u
#define CYREG_SFLASH_AV_PAIRS_8B005 0x0ffff085u
#define CYREG_SFLASH_AV_PAIRS_8B006 0x0ffff086u
#define CYREG_SFLASH_AV_PAIRS_8B007 0x0ffff087u
#define CYREG_SFLASH_AV_PAIRS_8B008 0x0ffff088u
#define CYREG_SFLASH_AV_PAIRS_8B009 0x0ffff089u
#define CYREG_SFLASH_AV_PAIRS_8B010 0x0ffff08au
#define CYREG_SFLASH_AV_PAIRS_8B011 0x0ffff08bu
#define CYREG_SFLASH_AV_PAIRS_8B012 0x0ffff08cu
#define CYREG_SFLASH_AV_PAIRS_8B013 0x0ffff08du
#define CYREG_SFLASH_AV_PAIRS_8B014 0x0ffff08eu
#define CYREG_SFLASH_AV_PAIRS_8B015 0x0ffff08fu
#define CYREG_SFLASH_AV_PAIRS_8B016 0x0ffff090u
#define CYREG_SFLASH_AV_PAIRS_8B017 0x0ffff091u
#define CYREG_SFLASH_AV_PAIRS_8B018 0x0ffff092u
#define CYREG_SFLASH_AV_PAIRS_8B019 0x0ffff093u
#define CYREG_SFLASH_AV_PAIRS_8B020 0x0ffff094u
#define CYREG_SFLASH_AV_PAIRS_8B021 0x0ffff095u
#define CYREG_SFLASH_AV_PAIRS_8B022 0x0ffff096u
#define CYREG_SFLASH_AV_PAIRS_8B023 0x0ffff097u
#define CYREG_SFLASH_AV_PAIRS_8B024 0x0ffff098u
#define CYREG_SFLASH_AV_PAIRS_8B025 0x0ffff099u
#define CYREG_SFLASH_AV_PAIRS_8B026 0x0ffff09au
#define CYREG_SFLASH_AV_PAIRS_8B027 0x0ffff09bu
#define CYREG_SFLASH_AV_PAIRS_8B028 0x0ffff09cu
#define CYREG_SFLASH_AV_PAIRS_8B029 0x0ffff09du
#define CYREG_SFLASH_AV_PAIRS_8B030 0x0ffff09eu
#define CYREG_SFLASH_AV_PAIRS_8B031 0x0ffff09fu
#define CYREG_SFLASH_AV_PAIRS_8B032 0x0ffff0a0u
#define CYREG_SFLASH_AV_PAIRS_8B033 0x0ffff0a1u
#define CYREG_SFLASH_AV_PAIRS_8B034 0x0ffff0a2u
#define CYREG_SFLASH_AV_PAIRS_8B035 0x0ffff0a3u
#define CYREG_SFLASH_AV_PAIRS_8B036 0x0ffff0a4u
#define CYREG_SFLASH_AV_PAIRS_8B037 0x0ffff0a5u
#define CYREG_SFLASH_AV_PAIRS_8B038 0x0ffff0a6u
#define CYREG_SFLASH_AV_PAIRS_8B039 0x0ffff0a7u
#define CYREG_SFLASH_AV_PAIRS_8B040 0x0ffff0a8u
#define CYREG_SFLASH_AV_PAIRS_8B041 0x0ffff0a9u
#define CYREG_SFLASH_AV_PAIRS_8B042 0x0ffff0aau
#define CYREG_SFLASH_AV_PAIRS_8B043 0x0ffff0abu
#define CYREG_SFLASH_AV_PAIRS_8B044 0x0ffff0acu
#define CYREG_SFLASH_AV_PAIRS_8B045 0x0ffff0adu
#define CYREG_SFLASH_AV_PAIRS_8B046 0x0ffff0aeu
#define CYREG_SFLASH_AV_PAIRS_8B047 0x0ffff0afu
#define CYREG_SFLASH_AV_PAIRS_8B048 0x0ffff0b0u
#define CYREG_SFLASH_AV_PAIRS_8B049 0x0ffff0b1u
#define CYREG_SFLASH_AV_PAIRS_8B050 0x0ffff0b2u
#define CYREG_SFLASH_AV_PAIRS_8B051 0x0ffff0b3u
#define CYREG_SFLASH_AV_PAIRS_8B052 0x0ffff0b4u
#define CYREG_SFLASH_AV_PAIRS_8B053 0x0ffff0b5u
#define CYREG_SFLASH_AV_PAIRS_8B054 0x0ffff0b6u
#define CYREG_SFLASH_AV_PAIRS_8B055 0x0ffff0b7u
#define CYREG_SFLASH_AV_PAIRS_8B056 0x0ffff0b8u
#define CYREG_SFLASH_AV_PAIRS_8B057 0x0ffff0b9u
#define CYREG_SFLASH_AV_PAIRS_8B058 0x0ffff0bau
#define CYREG_SFLASH_AV_PAIRS_8B059 0x0ffff0bbu
#define CYREG_SFLASH_AV_PAIRS_8B060 0x0ffff0bcu
#define CYREG_SFLASH_AV_PAIRS_8B061 0x0ffff0bdu
#define CYREG_SFLASH_AV_PAIRS_8B062 0x0ffff0beu
#define CYREG_SFLASH_AV_PAIRS_8B063 0x0ffff0bfu
#define CYREG_SFLASH_AV_PAIRS_8B064 0x0ffff0c0u
#define CYREG_SFLASH_AV_PAIRS_8B065 0x0ffff0c1u
#define CYREG_SFLASH_AV_PAIRS_8B066 0x0ffff0c2u
#define CYREG_SFLASH_AV_PAIRS_8B067 0x0ffff0c3u
#define CYREG_SFLASH_AV_PAIRS_8B068 0x0ffff0c4u
#define CYREG_SFLASH_AV_PAIRS_8B069 0x0ffff0c5u
#define CYREG_SFLASH_AV_PAIRS_8B070 0x0ffff0c6u
#define CYREG_SFLASH_AV_PAIRS_8B071 0x0ffff0c7u
#define CYREG_SFLASH_AV_PAIRS_8B072 0x0ffff0c8u
#define CYREG_SFLASH_AV_PAIRS_8B073 0x0ffff0c9u
#define CYREG_SFLASH_AV_PAIRS_8B074 0x0ffff0cau
#define CYREG_SFLASH_AV_PAIRS_8B075 0x0ffff0cbu
#define CYREG_SFLASH_AV_PAIRS_8B076 0x0ffff0ccu
#define CYREG_SFLASH_AV_PAIRS_8B077 0x0ffff0cdu
#define CYREG_SFLASH_AV_PAIRS_8B078 0x0ffff0ceu
#define CYREG_SFLASH_AV_PAIRS_8B079 0x0ffff0cfu
#define CYREG_SFLASH_AV_PAIRS_8B080 0x0ffff0d0u
#define CYREG_SFLASH_AV_PAIRS_8B081 0x0ffff0d1u
#define CYREG_SFLASH_AV_PAIRS_8B082 0x0ffff0d2u
#define CYREG_SFLASH_AV_PAIRS_8B083 0x0ffff0d3u
#define CYREG_SFLASH_AV_PAIRS_8B084 0x0ffff0d4u
#define CYREG_SFLASH_AV_PAIRS_8B085 0x0ffff0d5u
#define CYREG_SFLASH_AV_PAIRS_8B086 0x0ffff0d6u
#define CYREG_SFLASH_AV_PAIRS_8B087 0x0ffff0d7u
#define CYREG_SFLASH_AV_PAIRS_8B088 0x0ffff0d8u
#define CYREG_SFLASH_AV_PAIRS_8B089 0x0ffff0d9u
#define CYREG_SFLASH_AV_PAIRS_8B090 0x0ffff0dau
#define CYREG_SFLASH_AV_PAIRS_8B091 0x0ffff0dbu
#define CYREG_SFLASH_AV_PAIRS_8B092 0x0ffff0dcu
#define CYREG_SFLASH_AV_PAIRS_8B093 0x0ffff0ddu
#define CYREG_SFLASH_AV_PAIRS_8B094 0x0ffff0deu
#define CYREG_SFLASH_AV_PAIRS_8B095 0x0ffff0dfu
#define CYREG_SFLASH_AV_PAIRS_8B096 0x0ffff0e0u
#define CYREG_SFLASH_AV_PAIRS_8B097 0x0ffff0e1u
#define CYREG_SFLASH_AV_PAIRS_8B098 0x0ffff0e2u
#define CYREG_SFLASH_AV_PAIRS_8B099 0x0ffff0e3u
#define CYREG_SFLASH_AV_PAIRS_8B100 0x0ffff0e4u
#define CYREG_SFLASH_AV_PAIRS_8B101 0x0ffff0e5u
#define CYREG_SFLASH_AV_PAIRS_8B102 0x0ffff0e6u
#define CYREG_SFLASH_AV_PAIRS_8B103 0x0ffff0e7u
#define CYREG_SFLASH_AV_PAIRS_8B104 0x0ffff0e8u
#define CYREG_SFLASH_AV_PAIRS_8B105 0x0ffff0e9u
#define CYREG_SFLASH_AV_PAIRS_8B106 0x0ffff0eau
#define CYREG_SFLASH_AV_PAIRS_8B107 0x0ffff0ebu
#define CYREG_SFLASH_AV_PAIRS_8B108 0x0ffff0ecu
#define CYREG_SFLASH_AV_PAIRS_8B109 0x0ffff0edu
#define CYREG_SFLASH_AV_PAIRS_8B110 0x0ffff0eeu
#define CYREG_SFLASH_AV_PAIRS_8B111 0x0ffff0efu
#define CYREG_SFLASH_AV_PAIRS_8B112 0x0ffff0f0u
#define CYREG_SFLASH_AV_PAIRS_8B113 0x0ffff0f1u
#define CYREG_SFLASH_AV_PAIRS_8B114 0x0ffff0f2u
#define CYREG_SFLASH_AV_PAIRS_8B115 0x0ffff0f3u
#define CYREG_SFLASH_AV_PAIRS_8B116 0x0ffff0f4u
#define CYREG_SFLASH_AV_PAIRS_8B117 0x0ffff0f5u
#define CYREG_SFLASH_AV_PAIRS_8B118 0x0ffff0f6u
#define CYREG_SFLASH_AV_PAIRS_8B119 0x0ffff0f7u
#define CYREG_SFLASH_AV_PAIRS_8B120 0x0ffff0f8u
#define CYREG_SFLASH_AV_PAIRS_8B121 0x0ffff0f9u
#define CYREG_SFLASH_AV_PAIRS_8B122 0x0ffff0fau
#define CYREG_SFLASH_AV_PAIRS_8B123 0x0ffff0fbu
#define CYREG_SFLASH_AV_PAIRS_8B124 0x0ffff0fcu
#define CYREG_SFLASH_AV_PAIRS_8B125 0x0ffff0fdu
#define CYREG_SFLASH_AV_PAIRS_8B126 0x0ffff0feu
#define CYREG_SFLASH_AV_PAIRS_8B127 0x0ffff0ffu
#define CYREG_SFLASH_AV_PAIRS_32B00 0x0ffff100u
#define CYFLD_SFLASH_DATA32__OFFSET 0x00000000u
#define CYFLD_SFLASH_DATA32__SIZE 0x00000020u
#define CYREG_SFLASH_AV_PAIRS_32B01 0x0ffff104u
#define CYREG_SFLASH_AV_PAIRS_32B02 0x0ffff108u
#define CYREG_SFLASH_AV_PAIRS_32B03 0x0ffff10cu
#define CYREG_SFLASH_AV_PAIRS_32B04 0x0ffff110u
#define CYREG_SFLASH_AV_PAIRS_32B05 0x0ffff114u
#define CYREG_SFLASH_AV_PAIRS_32B06 0x0ffff118u
#define CYREG_SFLASH_AV_PAIRS_32B07 0x0ffff11cu
#define CYREG_SFLASH_AV_PAIRS_32B08 0x0ffff120u
#define CYREG_SFLASH_AV_PAIRS_32B09 0x0ffff124u
#define CYREG_SFLASH_AV_PAIRS_32B10 0x0ffff128u
#define CYREG_SFLASH_AV_PAIRS_32B11 0x0ffff12cu
#define CYREG_SFLASH_AV_PAIRS_32B12 0x0ffff130u
#define CYREG_SFLASH_AV_PAIRS_32B13 0x0ffff134u
#define CYREG_SFLASH_AV_PAIRS_32B14 0x0ffff138u
#define CYREG_SFLASH_AV_PAIRS_32B15 0x0ffff13cu
#define CYREG_SFLASH_CPUSS_WOUNDING 0x0ffff140u
#define CYREG_SFLASH_SILICON_ID 0x0ffff144u
#define CYFLD_SFLASH_ID__OFFSET 0x00000000u
#define CYFLD_SFLASH_ID__SIZE 0x00000010u
#define CYREG_SFLASH_CPUSS_PRIV_RAM 0x0ffff148u
#define CYREG_SFLASH_CPUSS_PRIV_FLASH 0x0ffff14cu
#define CYREG_SFLASH_HIB_KEY_DELAY 0x0ffff150u
#define CYFLD_SFLASH_WAKEUP_HOLDOFF__OFFSET 0x00000000u
#define CYFLD_SFLASH_WAKEUP_HOLDOFF__SIZE 0x0000000au
#define CYREG_SFLASH_DPSLP_KEY_DELAY 0x0ffff152u
#define CYREG_SFLASH_SWD_CONFIG 0x0ffff154u
#define CYFLD_SFLASH_SWD_SELECT__OFFSET 0x00000000u
#define CYFLD_SFLASH_SWD_SELECT__SIZE 0x00000001u
#define CYREG_SFLASH_SWD_LISTEN 0x0ffff158u
#define CYFLD_SFLASH_CYCLES__OFFSET 0x00000000u
#define CYFLD_SFLASH_CYCLES__SIZE 0x00000020u
#define CYREG_SFLASH_FLASH_START 0x0ffff15cu
#define CYFLD_SFLASH_ADDRESS__OFFSET 0x00000000u
#define CYFLD_SFLASH_ADDRESS__SIZE 0x00000020u
#define CYREG_SFLASH_CSD_TRIM1_HVIDAC 0x0ffff160u
#define CYFLD_SFLASH_TRIM8__OFFSET 0x00000000u
#define CYFLD_SFLASH_TRIM8__SIZE 0x00000008u
#define CYREG_SFLASH_CSD_TRIM2_HVIDAC 0x0ffff161u
#define CYREG_SFLASH_CSD_TRIM1_CSD 0x0ffff162u
#define CYREG_SFLASH_CSD_TRIM2_CSD 0x0ffff163u
#define CYREG_SFLASH_SAR_TEMP_MULTIPLIER 0x0ffff164u
#define CYFLD_SFLASH_TEMP_MULTIPLIER__OFFSET 0x00000000u
#define CYFLD_SFLASH_TEMP_MULTIPLIER__SIZE 0x00000010u
#define CYREG_SFLASH_SAR_TEMP_OFFSET 0x0ffff166u
#define CYFLD_SFLASH_TEMP_OFFSET__OFFSET 0x00000000u
#define CYFLD_SFLASH_TEMP_OFFSET__SIZE 0x00000010u
#define CYREG_SFLASH_SKIP_CHECKSUM 0x0ffff169u
#define CYFLD_SFLASH_SKIP__OFFSET 0x00000000u
#define CYFLD_SFLASH_SKIP__SIZE 0x00000008u
#define CYREG_SFLASH_PROT_VIRGINKEY0 0x0ffff170u
#define CYFLD_SFLASH_KEY8__OFFSET 0x00000000u
#define CYFLD_SFLASH_KEY8__SIZE 0x00000008u
#define CYREG_SFLASH_PROT_VIRGINKEY1 0x0ffff171u
#define CYREG_SFLASH_PROT_VIRGINKEY2 0x0ffff172u
#define CYREG_SFLASH_PROT_VIRGINKEY3 0x0ffff173u
#define CYREG_SFLASH_PROT_VIRGINKEY4 0x0ffff174u
#define CYREG_SFLASH_PROT_VIRGINKEY5 0x0ffff175u
#define CYREG_SFLASH_PROT_VIRGINKEY6 0x0ffff176u
#define CYREG_SFLASH_PROT_VIRGINKEY7 0x0ffff177u
#define CYREG_SFLASH_DIE_LOT0 0x0ffff178u
#define CYFLD_SFLASH_LOT__OFFSET 0x00000000u
#define CYFLD_SFLASH_LOT__SIZE 0x00000008u
#define CYREG_SFLASH_DIE_LOT1 0x0ffff179u
#define CYREG_SFLASH_DIE_LOT2 0x0ffff17au
#define CYREG_SFLASH_DIE_WAFER 0x0ffff17bu
#define CYFLD_SFLASH_WAFER__OFFSET 0x00000000u
#define CYFLD_SFLASH_WAFER__SIZE 0x00000008u
#define CYREG_SFLASH_DIE_X 0x0ffff17cu
#define CYFLD_SFLASH_X__OFFSET 0x00000000u
#define CYFLD_SFLASH_X__SIZE 0x00000006u
#define CYFLD_SFLASH_CRI_PASS__OFFSET 0x00000006u
#define CYFLD_SFLASH_CRI_PASS__SIZE 0x00000002u
#define CYREG_SFLASH_DIE_Y 0x0ffff17du
#define CYFLD_SFLASH_Y__OFFSET 0x00000000u
#define CYFLD_SFLASH_Y__SIZE 0x00000006u
#define CYFLD_SFLASH_CHI_PASS__OFFSET 0x00000006u
#define CYFLD_SFLASH_CHI_PASS__SIZE 0x00000002u
#define CYREG_SFLASH_DIE_SORT 0x0ffff17eu
#define CYFLD_SFLASH_S1_PASS__OFFSET 0x00000000u
#define CYFLD_SFLASH_S1_PASS__SIZE 0x00000002u
#define CYFLD_SFLASH_S2_PASS__OFFSET 0x00000002u
#define CYFLD_SFLASH_S2_PASS__SIZE 0x00000002u
#define CYFLD_SFLASH_S3_PASS__OFFSET 0x00000004u
#define CYFLD_SFLASH_S3_PASS__SIZE 0x00000002u
#define CYREG_SFLASH_DIE_MINOR 0x0ffff17fu
#define CYFLD_SFLASH_MINOR__OFFSET 0x00000000u
#define CYFLD_SFLASH_MINOR__SIZE 0x00000008u
#define CYREG_SFLASH_PE_TE_DATA00 0x0ffff180u
#define CYREG_SFLASH_PE_TE_DATA01 0x0ffff181u
#define CYREG_SFLASH_PE_TE_DATA02 0x0ffff182u
#define CYREG_SFLASH_PE_TE_DATA03 0x0ffff183u
#define CYREG_SFLASH_PE_TE_DATA04 0x0ffff184u
#define CYREG_SFLASH_PE_TE_DATA05 0x0ffff185u
#define CYREG_SFLASH_PE_TE_DATA06 0x0ffff186u
#define CYREG_SFLASH_PE_TE_DATA07 0x0ffff187u
#define CYREG_SFLASH_PE_TE_DATA08 0x0ffff188u
#define CYREG_SFLASH_PE_TE_DATA09 0x0ffff189u
#define CYREG_SFLASH_PE_TE_DATA10 0x0ffff18au
#define CYREG_SFLASH_PE_TE_DATA11 0x0ffff18bu
#define CYREG_SFLASH_PE_TE_DATA12 0x0ffff18cu
#define CYREG_SFLASH_PE_TE_DATA13 0x0ffff18du
#define CYREG_SFLASH_PE_TE_DATA14 0x0ffff18eu
#define CYREG_SFLASH_PE_TE_DATA15 0x0ffff18fu
#define CYREG_SFLASH_PE_TE_DATA16 0x0ffff190u
#define CYREG_SFLASH_PE_TE_DATA17 0x0ffff191u
#define CYREG_SFLASH_PE_TE_DATA18 0x0ffff192u
#define CYREG_SFLASH_PE_TE_DATA19 0x0ffff193u
#define CYREG_SFLASH_PE_TE_DATA20 0x0ffff194u
#define CYREG_SFLASH_PE_TE_DATA21 0x0ffff195u
#define CYREG_SFLASH_PE_TE_DATA22 0x0ffff196u
#define CYREG_SFLASH_PE_TE_DATA23 0x0ffff197u
#define CYREG_SFLASH_PE_TE_DATA24 0x0ffff198u
#define CYREG_SFLASH_PE_TE_DATA25 0x0ffff199u
#define CYREG_SFLASH_PE_TE_DATA26 0x0ffff19au
#define CYREG_SFLASH_PE_TE_DATA27 0x0ffff19bu
#define CYREG_SFLASH_PE_TE_DATA28 0x0ffff19cu
#define CYREG_SFLASH_PE_TE_DATA29 0x0ffff19du
#define CYREG_SFLASH_PE_TE_DATA30 0x0ffff19eu
#define CYREG_SFLASH_PE_TE_DATA31 0x0ffff19fu
#define CYREG_SFLASH_PP 0x0ffff1a0u
#define CYFLD_SFLASH_PERIOD__OFFSET 0x00000000u
#define CYFLD_SFLASH_PERIOD__SIZE 0x00000018u
#define CYFLD_SFLASH_PDAC__OFFSET 0x00000018u
#define CYFLD_SFLASH_PDAC__SIZE 0x00000004u
#define CYFLD_SFLASH_NDAC__OFFSET 0x0000001cu
#define CYFLD_SFLASH_NDAC__SIZE 0x00000004u
#define CYREG_SFLASH_E 0x0ffff1a4u
#define CYREG_SFLASH_P 0x0ffff1a8u
#define CYREG_SFLASH_EA_E 0x0ffff1acu
#define CYREG_SFLASH_EA_P 0x0ffff1b0u
#define CYREG_SFLASH_ES_E 0x0ffff1b4u
#define CYREG_SFLASH_ES_P_EO 0x0ffff1b8u
#define CYREG_SFLASH_E_VCTAT 0x0ffff1bcu
#define CYFLD_SFLASH_VCTAT_SLOPE__OFFSET 0x00000000u
#define CYFLD_SFLASH_VCTAT_SLOPE__SIZE 0x00000004u
#define CYFLD_SFLASH_VCTAT_VOLTAGE__OFFSET 0x00000004u
#define CYFLD_SFLASH_VCTAT_VOLTAGE__SIZE 0x00000002u
#define CYFLD_SFLASH_VCTAT_ENABLE__OFFSET 0x00000006u
#define CYFLD_SFLASH_VCTAT_ENABLE__SIZE 0x00000001u
#define CYREG_SFLASH_P_VCTAT 0x0ffff1bdu
#define CYREG_SFLASH_MARGIN 0x0ffff1beu
#define CYFLD_SFLASH_MDAC__OFFSET 0x00000000u
#define CYFLD_SFLASH_MDAC__SIZE 0x00000008u
#define CYREG_SFLASH_SPCIF_TRIM1 0x0ffff1bfu
#define CYFLD_SFLASH_BDAC__OFFSET 0x00000000u
#define CYFLD_SFLASH_BDAC__SIZE 0x00000004u
#define CYREG_SFLASH_IMO_MAXF0 0x0ffff1c0u
#define CYFLD_SFLASH_MAXFREQ__OFFSET 0x00000000u
#define CYFLD_SFLASH_MAXFREQ__SIZE 0x00000006u
#define CYREG_SFLASH_IMO_ABS0 0x0ffff1c1u
#define CYFLD_SFLASH_ABS_TRIM_IMO__OFFSET 0x00000000u
#define CYFLD_SFLASH_ABS_TRIM_IMO__SIZE 0x00000006u
#define CYREG_SFLASH_IMO_TMPCO0 0x0ffff1c2u
#define CYFLD_SFLASH_TMPCO_TRIM_IMO__OFFSET 0x00000000u
#define CYFLD_SFLASH_TMPCO_TRIM_IMO__SIZE 0x00000006u
#define CYREG_SFLASH_IMO_MAXF1 0x0ffff1c3u
#define CYREG_SFLASH_IMO_ABS1 0x0ffff1c4u
#define CYREG_SFLASH_IMO_TMPCO1 0x0ffff1c5u
#define CYREG_SFLASH_IMO_MAXF2 0x0ffff1c6u
#define CYREG_SFLASH_IMO_ABS2 0x0ffff1c7u
#define CYREG_SFLASH_IMO_TMPCO2 0x0ffff1c8u
#define CYREG_SFLASH_IMO_MAXF3 0x0ffff1c9u
#define CYREG_SFLASH_IMO_ABS3 0x0ffff1cau
#define CYREG_SFLASH_IMO_TMPCO3 0x0ffff1cbu
#define CYREG_SFLASH_IMO_ABS4 0x0ffff1ccu
#define CYREG_SFLASH_IMO_TMPCO4 0x0ffff1cdu
#define CYREG_SFLASH_IMO_TRIM00 0x0ffff1d0u
#define CYFLD_SFLASH_OFFSET__OFFSET 0x00000000u
#define CYFLD_SFLASH_OFFSET__SIZE 0x00000008u
#define CYREG_SFLASH_IMO_TRIM01 0x0ffff1d1u
#define CYREG_SFLASH_IMO_TRIM02 0x0ffff1d2u
#define CYREG_SFLASH_IMO_TRIM03 0x0ffff1d3u
#define CYREG_SFLASH_IMO_TRIM04 0x0ffff1d4u
#define CYREG_SFLASH_IMO_TRIM05 0x0ffff1d5u
#define CYREG_SFLASH_IMO_TRIM06 0x0ffff1d6u
#define CYREG_SFLASH_IMO_TRIM07 0x0ffff1d7u
#define CYREG_SFLASH_IMO_TRIM08 0x0ffff1d8u
#define CYREG_SFLASH_IMO_TRIM09 0x0ffff1d9u
#define CYREG_SFLASH_IMO_TRIM10 0x0ffff1dau
#define CYREG_SFLASH_IMO_TRIM11 0x0ffff1dbu
#define CYREG_SFLASH_IMO_TRIM12 0x0ffff1dcu
#define CYREG_SFLASH_IMO_TRIM13 0x0ffff1ddu
#define CYREG_SFLASH_IMO_TRIM14 0x0ffff1deu
#define CYREG_SFLASH_IMO_TRIM15 0x0ffff1dfu
#define CYREG_SFLASH_IMO_TRIM16 0x0ffff1e0u
#define CYREG_SFLASH_IMO_TRIM17 0x0ffff1e1u
#define CYREG_SFLASH_IMO_TRIM18 0x0ffff1e2u
#define CYREG_SFLASH_IMO_TRIM19 0x0ffff1e3u
#define CYREG_SFLASH_IMO_TRIM20 0x0ffff1e4u
#define CYREG_SFLASH_IMO_TRIM21 0x0ffff1e5u
#define CYREG_SFLASH_IMO_TRIM22 0x0ffff1e6u
#define CYREG_SFLASH_IMO_TRIM23 0x0ffff1e7u
#define CYREG_SFLASH_IMO_TRIM24 0x0ffff1e8u
#define CYREG_SFLASH_IMO_TRIM25 0x0ffff1e9u
#define CYREG_SFLASH_IMO_TRIM26 0x0ffff1eau
#define CYREG_SFLASH_IMO_TRIM27 0x0ffff1ebu
#define CYREG_SFLASH_IMO_TRIM28 0x0ffff1ecu
#define CYREG_SFLASH_IMO_TRIM29 0x0ffff1edu
#define CYREG_SFLASH_IMO_TRIM30 0x0ffff1eeu
#define CYREG_SFLASH_IMO_TRIM31 0x0ffff1efu
#define CYREG_SFLASH_IMO_TRIM32 0x0ffff1f0u
#define CYREG_SFLASH_IMO_TRIM33 0x0ffff1f1u
#define CYREG_SFLASH_IMO_TRIM34 0x0ffff1f2u
#define CYREG_SFLASH_IMO_TRIM35 0x0ffff1f3u
#define CYREG_SFLASH_IMO_TRIM36 0x0ffff1f4u
#define CYREG_SFLASH_IMO_TRIM37 0x0ffff1f5u
#define CYREG_SFLASH_IMO_TRIM38 0x0ffff1f6u
#define CYREG_SFLASH_IMO_TRIM39 0x0ffff1f7u
#define CYREG_SFLASH_IMO_TRIM40 0x0ffff1f8u
#define CYREG_SFLASH_IMO_TRIM41 0x0ffff1f9u
#define CYREG_SFLASH_IMO_TRIM42 0x0ffff1fau
#define CYREG_SFLASH_IMO_TRIM43 0x0ffff1fbu
#define CYREG_SFLASH_IMO_TRIM44 0x0ffff1fcu
#define CYREG_SFLASH_IMO_TRIM45 0x0ffff1fdu
#define CYREG_SFLASH_CHECKSUM 0x0ffff1feu
#define CYFLD_SFLASH_CHECKSUM__OFFSET 0x00000000u
#define CYFLD_SFLASH_CHECKSUM__SIZE 0x00000010u
#define CYDEV_SROM_BASE 0x10000000u
#define CYDEV_SROM_SIZE 0x00001000u
#define CYREG_SROM_DATA_MBASE 0x10000000u
#define CYREG_SROM_DATA_MSIZE 0x00001000u
#define CYDEV_SRAM_BASE 0x20000000u
#define CYDEV_SRAM_SIZE 0x00001000u
#define CYREG_SRAM_DATA_MBASE 0x20000000u
#define CYREG_SRAM_DATA_MSIZE 0x00001000u
#define CYDEV_CPUSS_BASE 0x40000000u
#define CYDEV_CPUSS_SIZE 0x00010000u
#define CYREG_CPUSS_CONFIG 0x40000000u
#define CYFLD_CPUSS_VECS_IN_RAM__OFFSET 0x00000000u
#define CYFLD_CPUSS_VECS_IN_RAM__SIZE 0x00000001u
#define CYFLD_CPUSS_FLSH_ACC_BYPASS__OFFSET 0x00000001u
#define CYFLD_CPUSS_FLSH_ACC_BYPASS__SIZE 0x00000001u
#define CYREG_CPUSS_SYSREQ 0x40000004u
#define CYFLD_CPUSS_COMMAND__OFFSET 0x00000000u
#define CYFLD_CPUSS_COMMAND__SIZE 0x00000010u
#define CYFLD_CPUSS_NO_RST_OVR__OFFSET 0x0000001bu
#define CYFLD_CPUSS_NO_RST_OVR__SIZE 0x00000001u
#define CYFLD_CPUSS_PRIVILEGED__OFFSET 0x0000001cu
#define CYFLD_CPUSS_PRIVILEGED__SIZE 0x00000001u
#define CYFLD_CPUSS_ROM_ACCESS_EN__OFFSET 0x0000001du
#define CYFLD_CPUSS_ROM_ACCESS_EN__SIZE 0x00000001u
#define CYFLD_CPUSS_HMASTER__OFFSET 0x0000001eu
#define CYFLD_CPUSS_HMASTER__SIZE 0x00000001u
#define CYFLD_CPUSS_SYSREQ__OFFSET 0x0000001fu
#define CYFLD_CPUSS_SYSREQ__SIZE 0x00000001u
#define CYREG_CPUSS_SYSARG 0x40000008u
#define CYFLD_CPUSS_ARG32__OFFSET 0x00000000u
#define CYFLD_CPUSS_ARG32__SIZE 0x00000020u
#define CYREG_CPUSS_PROTECTION 0x4000000cu
#define CYFLD_CPUSS_PROT__OFFSET 0x00000000u
#define CYFLD_CPUSS_PROT__SIZE 0x00000004u
#define CYVAL_CPUSS_PROT_VIRGIN 0x00000000u
#define CYVAL_CPUSS_PROT_OPEN 0x00000001u
#define CYVAL_CPUSS_PROT_PROTECTED 0x00000002u
#define CYVAL_CPUSS_PROT_KILL 0x00000004u
#define CYVAL_CPUSS_PROT_BOOT 0x00000008u
#define CYFLD_CPUSS_PROT_LOCK__OFFSET 0x0000001fu
#define CYFLD_CPUSS_PROT_LOCK__SIZE 0x00000001u
#define CYREG_CPUSS_PRIV_ROM 0x40000010u
#define CYFLD_CPUSS_ROM_LIMIT__OFFSET 0x00000000u
#define CYFLD_CPUSS_ROM_LIMIT__SIZE 0x00000008u
#define CYREG_CPUSS_PRIV_RAM 0x40000014u
#define CYFLD_CPUSS_RAM_LIMIT__OFFSET 0x00000000u
#define CYFLD_CPUSS_RAM_LIMIT__SIZE 0x00000009u
#define CYREG_CPUSS_PRIV_FLASH 0x40000018u
#define CYFLD_CPUSS_FLASH_LIMIT__OFFSET 0x00000000u
#define CYFLD_CPUSS_FLASH_LIMIT__SIZE 0x0000000bu
#define CYREG_CPUSS_WOUNDING 0x4000001cu
#define CYFLD_CPUSS_RAM_SIZE__OFFSET 0x00000000u
#define CYFLD_CPUSS_RAM_SIZE__SIZE 0x00000009u
#define CYFLD_CPUSS_RAM_WOUND__OFFSET 0x00000010u
#define CYFLD_CPUSS_RAM_WOUND__SIZE 0x00000003u
#define CYVAL_CPUSS_RAM_WOUND_FULL 0x00000000u
#define CYVAL_CPUSS_RAM_WOUND_DIV_BY_2 0x00000001u
#define CYVAL_CPUSS_RAM_WOUND_DIV_BY_4 0x00000002u
#define CYVAL_CPUSS_RAM_WOUND_DIV_BY_8 0x00000003u
#define CYVAL_CPUSS_RAM_WOUND_DIV_BY_16 0x00000004u
#define CYVAL_CPUSS_RAM_WOUND_DIV_BY_32 0x00000005u
#define CYVAL_CPUSS_RAM_WOUND_DIV_BY_64 0x00000006u
#define CYVAL_CPUSS_RAM_WOUND_DIV_BY_128 0x00000007u
#define CYFLD_CPUSS_FLASH_WOUND__OFFSET 0x00000014u
#define CYFLD_CPUSS_FLASH_WOUND__SIZE 0x00000003u
#define CYVAL_CPUSS_FLASH_WOUND_FULL 0x00000000u
#define CYVAL_CPUSS_FLASH_WOUND_DIV_BY_2 0x00000001u
#define CYVAL_CPUSS_FLASH_WOUND_DIV_BY_4 0x00000002u
#define CYVAL_CPUSS_FLASH_WOUND_DIV_BY_8 0x00000003u
#define CYVAL_CPUSS_FLASH_WOUND_DIV_BY_16 0x00000004u
#define CYVAL_CPUSS_FLASH_WOUND_DIV_BY_32 0x00000005u
#define CYVAL_CPUSS_FLASH_WOUND_DIV_BY_64 0x00000006u
#define CYVAL_CPUSS_FLASH_WOUND_DIV_BY_128 0x00000007u
#define CYREG_CPUSS_INTR_SELECT 0x40000020u
#define CYFLD_CPUSS_SELECT32__OFFSET 0x00000000u
#define CYFLD_CPUSS_SELECT32__SIZE 0x00000020u
#define CYDEV_HSIOM_BASE 0x40010000u
#define CYDEV_HSIOM_SIZE 0x00001000u
#define CYREG_HSIOM_PORT_SEL0 0x40010000u
#define CYFLD_HSIOM_SEL0__OFFSET 0x00000000u
#define CYFLD_HSIOM_SEL0__SIZE 0x00000004u
#define CYVAL_HSIOM_SEL0_GPIO 0x00000000u
#define CYVAL_HSIOM_SEL0_GPIO_DSI 0x00000001u
#define CYVAL_HSIOM_SEL0_DSI_DSI 0x00000002u
#define CYVAL_HSIOM_SEL0_DSI_GPIO 0x00000003u
#define CYVAL_HSIOM_SEL0_CSD_SENSE 0x00000004u
#define CYVAL_HSIOM_SEL0_CSD_SHIELD 0x00000005u
#define CYVAL_HSIOM_SEL0_AMUXA 0x00000006u
#define CYVAL_HSIOM_SEL0_AMUXB 0x00000007u
#define CYVAL_HSIOM_SEL0_ACT_0 0x00000008u
#define CYVAL_HSIOM_SEL0_ACT_1 0x00000009u
#define CYVAL_HSIOM_SEL0_ACT_2 0x0000000au
#define CYVAL_HSIOM_SEL0_ACT_3 0x0000000bu
#define CYVAL_HSIOM_SEL0_LCD_COM 0x0000000cu
#define CYVAL_HSIOM_SEL0_LCD_SEG 0x0000000du
#define CYVAL_HSIOM_SEL0_DPSLP_0 0x0000000eu
#define CYVAL_HSIOM_SEL0_DPSLP_1 0x0000000fu
#define CYVAL_HSIOM_SEL0_COMP1_INP 0x00000000u
#define CYVAL_HSIOM_SEL0_SCB0_SPI_SSEL1 0x0000000fu
#define CYFLD_HSIOM_SEL1__OFFSET 0x00000004u
#define CYFLD_HSIOM_SEL1__SIZE 0x00000004u
#define CYVAL_HSIOM_SEL1_COMP1_INN 0x00000000u
#define CYVAL_HSIOM_SEL1_SCB0_SPI_SSEL2 0x0000000fu
#define CYFLD_HSIOM_SEL2__OFFSET 0x00000008u
#define CYFLD_HSIOM_SEL2__SIZE 0x00000004u
#define CYVAL_HSIOM_SEL2_COMP2_INP 0x00000000u
#define CYVAL_HSIOM_SEL2_SCB0_SPI_SSEL3 0x0000000fu
#define CYFLD_HSIOM_SEL3__OFFSET 0x0000000cu
#define CYFLD_HSIOM_SEL3__SIZE 0x00000004u
#define CYVAL_HSIOM_SEL3_COMP2_INN 0x00000000u
#define CYFLD_HSIOM_SEL4__OFFSET 0x00000010u
#define CYFLD_HSIOM_SEL4__SIZE 0x00000004u
#define CYVAL_HSIOM_SEL4_SCB1_UART_RX 0x00000009u
#define CYVAL_HSIOM_SEL4_SCB1_I2C_SCL 0x0000000eu
#define CYVAL_HSIOM_SEL4_SCB1_SPI_MOSI 0x0000000fu
#define CYFLD_HSIOM_SEL5__OFFSET 0x00000014u
#define CYFLD_HSIOM_SEL5__SIZE 0x00000004u
#define CYVAL_HSIOM_SEL5_SCB1_UART_TX 0x00000009u
#define CYVAL_HSIOM_SEL5_SCB1_I2C_SDA 0x0000000eu
#define CYVAL_HSIOM_SEL5_SCB1_SPI_MISO 0x0000000fu
#define CYFLD_HSIOM_SEL6__OFFSET 0x00000018u
#define CYFLD_HSIOM_SEL6__SIZE 0x00000004u
#define CYVAL_HSIOM_SEL6_EXT_CLK 0x00000008u
#define CYVAL_HSIOM_SEL6_SCB1_SPI_CLK 0x0000000fu
#define CYFLD_HSIOM_SEL7__OFFSET 0x0000001cu
#define CYFLD_HSIOM_SEL7__SIZE 0x00000004u
#define CYVAL_HSIOM_SEL7_WAKEUP 0x0000000eu
#define CYVAL_HSIOM_SEL7_SCB1_SPI_SSEL0 0x0000000fu
#define CYREG_HSIOM_PORT_SEL1 0x40010004u
#define CYREG_HSIOM_PORT_SEL2 0x40010008u
#define CYREG_HSIOM_PORT_SEL3 0x4001000cu
#define CYREG_HSIOM_PORT_SEL4 0x40010010u
#define CYDEV_CLK_BASE 0x40020000u
#define CYDEV_CLK_SIZE 0x00010000u
#define CYREG_CLK_DIVIDER_A00 0x40020000u
#define CYFLD_CLK_DIVIDER_A__OFFSET 0x00000000u
#define CYFLD_CLK_DIVIDER_A__SIZE 0x00000010u
#define CYFLD_CLK_ENABLE_A__OFFSET 0x0000001fu
#define CYFLD_CLK_ENABLE_A__SIZE 0x00000001u
#define CYREG_CLK_DIVIDER_A01 0x40020004u
#define CYREG_CLK_DIVIDER_A02 0x40020008u
#define CYREG_CLK_DIVIDER_B00 0x40020040u
#define CYFLD_CLK_DIVIDER_B__OFFSET 0x00000000u
#define CYFLD_CLK_DIVIDER_B__SIZE 0x00000010u
#define CYFLD_CLK_CASCADE_A_B__OFFSET 0x0000001eu
#define CYFLD_CLK_CASCADE_A_B__SIZE 0x00000001u
#define CYFLD_CLK_ENABLE_B__OFFSET 0x0000001fu
#define CYFLD_CLK_ENABLE_B__SIZE 0x00000001u
#define CYREG_CLK_DIVIDER_B01 0x40020044u
#define CYREG_CLK_DIVIDER_B02 0x40020048u
#define CYREG_CLK_DIVIDER_C00 0x40020080u
#define CYFLD_CLK_DIVIDER_C__OFFSET 0x00000000u
#define CYFLD_CLK_DIVIDER_C__SIZE 0x00000010u
#define CYFLD_CLK_CASCADE_B_C__OFFSET 0x0000001eu
#define CYFLD_CLK_CASCADE_B_C__SIZE 0x00000001u
#define CYFLD_CLK_ENABLE_C__OFFSET 0x0000001fu
#define CYFLD_CLK_ENABLE_C__SIZE 0x00000001u
#define CYREG_CLK_DIVIDER_C01 0x40020084u
#define CYREG_CLK_DIVIDER_C02 0x40020088u
#define CYREG_CLK_DIVIDER_FRAC_A00 0x40020100u
#define CYFLD_CLK_FRAC_A__OFFSET 0x00000010u
#define CYFLD_CLK_FRAC_A__SIZE 0x00000005u
#define CYREG_CLK_DIVIDER_FRAC_B00 0x40020140u
#define CYFLD_CLK_FRAC_B__OFFSET 0x00000010u
#define CYFLD_CLK_FRAC_B__SIZE 0x00000005u
#define CYREG_CLK_DIVIDER_FRAC_C00 0x40020180u
#define CYFLD_CLK_FRAC_C__OFFSET 0x00000010u
#define CYFLD_CLK_FRAC_C__SIZE 0x00000005u
#define CYREG_CLK_SELECT00 0x40020200u
#define CYFLD_CLK_DIVIDER_N__OFFSET 0x00000000u
#define CYFLD_CLK_DIVIDER_N__SIZE 0x00000004u
#define CYFLD_CLK_DIVIDER_ABC__OFFSET 0x00000004u
#define CYFLD_CLK_DIVIDER_ABC__SIZE 0x00000002u
#define CYVAL_CLK_DIVIDER_ABC_OFF 0x00000000u
#define CYVAL_CLK_DIVIDER_ABC_A 0x00000001u
#define CYVAL_CLK_DIVIDER_ABC_B 0x00000002u
#define CYVAL_CLK_DIVIDER_ABC_C 0x00000003u
#define CYREG_CLK_SELECT01 0x40020204u
#define CYREG_CLK_SELECT02 0x40020208u
#define CYREG_CLK_SELECT03 0x4002020cu
#define CYREG_CLK_SELECT04 0x40020210u
#define CYREG_CLK_SELECT05 0x40020214u
#define CYREG_CLK_SELECT06 0x40020218u
#define CYREG_CLK_SELECT07 0x4002021cu
#define CYREG_CLK_SELECT08 0x40020220u
#define CYREG_CLK_SELECT09 0x40020224u
#define CYREG_CLK_SELECT10 0x40020228u
#define CYREG_CLK_SELECT11 0x4002022cu
#define CYREG_CLK_SELECT12 0x40020230u
#define CYREG_CLK_SELECT13 0x40020234u
#define CYREG_CLK_SELECT14 0x40020238u
#define CYREG_CLK_SELECT15 0x4002023cu
#define CYDEV_TST_BASE 0x40030000u
#define CYDEV_TST_SIZE 0x00010000u
#define CYREG_TST_CTRL 0x40030000u
#define CYFLD_TST_DAP_NO_ACCESS__OFFSET 0x00000000u
#define CYFLD_TST_DAP_NO_ACCESS__SIZE 0x00000001u
#define CYFLD_TST_DAP_NO_DEBUG__OFFSET 0x00000001u
#define CYFLD_TST_DAP_NO_DEBUG__SIZE 0x00000001u
#define CYFLD_TST_SWD_CONNECTED__OFFSET 0x00000002u
#define CYFLD_TST_SWD_CONNECTED__SIZE 0x00000001u
#define CYFLD_TST_TEST_RESET_EN_N__OFFSET 0x00000008u
#define CYFLD_TST_TEST_RESET_EN_N__SIZE 0x00000001u
#define CYFLD_TST_TEST_SET_EN_N__OFFSET 0x00000009u
#define CYFLD_TST_TEST_SET_EN_N__SIZE 0x00000001u
#define CYFLD_TST_TEST_ICG_EN_N__OFFSET 0x0000000au
#define CYFLD_TST_TEST_ICG_EN_N__SIZE 0x00000001u
#define CYFLD_TST_TEST_OCC0_1_EN_N__OFFSET 0x0000000bu
#define CYFLD_TST_TEST_OCC0_1_EN_N__SIZE 0x00000001u
#define CYFLD_TST_TEST_OCC0_2_EN_N__OFFSET 0x0000000cu
#define CYFLD_TST_TEST_OCC0_2_EN_N__SIZE 0x00000001u
#define CYFLD_TST_TEST_SLPISOLATE_EN__OFFSET 0x0000000du
#define CYFLD_TST_TEST_SLPISOLATE_EN__SIZE 0x00000001u
#define CYFLD_TST_TEST_SYSISOLATE_EN__OFFSET 0x0000000eu
#define CYFLD_TST_TEST_SYSISOLATE_EN__SIZE 0x00000001u
#define CYFLD_TST_TEST_SLPRETAIN_EN__OFFSET 0x0000000fu
#define CYFLD_TST_TEST_SLPRETAIN_EN__SIZE 0x00000001u
#define CYFLD_TST_TEST_SYSRETAIN_EN__OFFSET 0x00000010u
#define CYFLD_TST_TEST_SYSRETAIN_EN__SIZE 0x00000001u
#define CYFLD_TST_TEST_SPARE1_EN__OFFSET 0x00000011u
#define CYFLD_TST_TEST_SPARE1_EN__SIZE 0x00000001u
#define CYFLD_TST_TEST_SPARE2_EN__OFFSET 0x00000012u
#define CYFLD_TST_TEST_SPARE2_EN__SIZE 0x00000001u
#define CYFLD_TST_SCAN_OCC_OBSERVE__OFFSET 0x00000018u
#define CYFLD_TST_SCAN_OCC_OBSERVE__SIZE 0x00000001u
#define CYFLD_TST_SCAN_TRF1__OFFSET 0x00000019u
#define CYFLD_TST_SCAN_TRF1__SIZE 0x00000001u
#define CYFLD_TST_SCAN_TRF__OFFSET 0x0000001au
#define CYFLD_TST_SCAN_TRF__SIZE 0x00000001u
#define CYFLD_TST_SCAN_IDDQ__OFFSET 0x0000001bu
#define CYFLD_TST_SCAN_IDDQ__SIZE 0x00000001u
#define CYFLD_TST_SCAN_COMPRESS__OFFSET 0x0000001cu
#define CYFLD_TST_SCAN_COMPRESS__SIZE 0x00000001u
#define CYFLD_TST_SCAN_MODE__OFFSET 0x0000001du
#define CYFLD_TST_SCAN_MODE__SIZE 0x00000001u
#define CYFLD_TST_PTM_MODE_EN__OFFSET 0x0000001eu
#define CYFLD_TST_PTM_MODE_EN__SIZE 0x00000001u
#define CYREG_TST_ADFT_CTRL 0x40030004u
#define CYFLD_TST_ENABLE__OFFSET 0x0000001fu
#define CYFLD_TST_ENABLE__SIZE 0x00000001u
#define CYREG_TST_DDFT_CTRL 0x40030008u
#define CYFLD_TST_DFT_SEL1__OFFSET 0x00000000u
#define CYFLD_TST_DFT_SEL1__SIZE 0x00000006u
#define CYVAL_TST_DFT_SEL1_VSS 0x00000000u
#define CYVAL_TST_DFT_SEL1_CLK1 0x00000001u
#define CYVAL_TST_DFT_SEL1_CLK2 0x00000002u
#define CYVAL_TST_DFT_SEL1_PWR1 0x00000003u
#define CYVAL_TST_DFT_SEL1_PWR2 0x00000004u
#define CYVAL_TST_DFT_SEL1_VMON 0x00000005u
#define CYVAL_TST_DFT_SEL1_TSS_VDDA_OK 0x00000006u
#define CYVAL_TST_DFT_SEL1_ADFT_TRIP1 0x00000007u
#define CYVAL_TST_DFT_SEL1_ADFT_TRIP2 0x00000008u
#define CYVAL_TST_DFT_SEL1_TSS1 0x00000009u
#define CYVAL_TST_DFT_SEL1_TSS2 0x0000000au
#define CYVAL_TST_DFT_SEL1_TSS3 0x0000000bu
#define CYVAL_TST_DFT_SEL1_TSS4 0x0000000cu
#define CYVAL_TST_DFT_SEL1_I2CS_CLK_I2CS 0x0000000du
#define CYVAL_TST_DFT_SEL1_I2CS_SDAIN_SI 0x0000000eu
#define CYFLD_TST_DFT_SEL2__OFFSET 0x00000008u
#define CYFLD_TST_DFT_SEL2__SIZE 0x00000006u
#define CYVAL_TST_DFT_SEL2_VSS 0x00000000u
#define CYVAL_TST_DFT_SEL2_CLK1 0x00000001u
#define CYVAL_TST_DFT_SEL2_CLK2 0x00000002u
#define CYVAL_TST_DFT_SEL2_PWR1 0x00000003u
#define CYVAL_TST_DFT_SEL2_PWR2 0x00000004u
#define CYVAL_TST_DFT_SEL2_VMON 0x00000005u
#define CYVAL_TST_DFT_SEL2_TSS_VDDA_OK 0x00000006u
#define CYVAL_TST_DFT_SEL2_ADFT_TRIP1 0x00000007u
#define CYVAL_TST_DFT_SEL2_ADFT_TRIP2 0x00000008u
#define CYVAL_TST_DFT_SEL2_TSS1 0x00000009u
#define CYVAL_TST_DFT_SEL2_TSS2 0x0000000au
#define CYVAL_TST_DFT_SEL2_TSS3 0x0000000bu
#define CYVAL_TST_DFT_SEL2_TSS4 0x0000000cu
#define CYVAL_TST_DFT_SEL2_I2CS_CLK_I2CS 0x0000000du
#define CYVAL_TST_DFT_SEL2_I2CS_SDAIN_SI 0x0000000eu
#define CYFLD_TST_EDGE__OFFSET 0x0000001cu
#define CYFLD_TST_EDGE__SIZE 0x00000001u
#define CYVAL_TST_EDGE_POSEDGE 0x00000000u
#define CYVAL_TST_EDGE_NEGEDGE 0x00000001u
#define CYFLD_TST_DIVIDE__OFFSET 0x0000001du
#define CYFLD_TST_DIVIDE__SIZE 0x00000002u
#define CYVAL_TST_DIVIDE_DIRECT 0x00000000u
#define CYVAL_TST_DIVIDE_DIV_BY_2 0x00000001u
#define CYVAL_TST_DIVIDE_DIV_BY_4 0x00000002u
#define CYVAL_TST_DIVIDE_DIV_BY_8 0x00000003u
#define CYREG_TST_MODE 0x40030014u
#define CYFLD_TST_TEST_MODE__OFFSET 0x0000001fu
#define CYFLD_TST_TEST_MODE__SIZE 0x00000001u
#define CYREG_TST_TRIM_CNTR1 0x40030018u
#define CYFLD_TST_COUNTER__OFFSET 0x00000000u
#define CYFLD_TST_COUNTER__SIZE 0x00000010u
#define CYFLD_TST_COUNTER_DONE__OFFSET 0x0000001fu
#define CYFLD_TST_COUNTER_DONE__SIZE 0x00000001u
#define CYREG_TST_TRIM_CNTR2 0x4003001cu
#define CYDEV_PRT0_BASE 0x40040000u
#define CYDEV_PRT0_SIZE 0x00000100u
#define CYREG_PRT0_DR 0x40040000u
#define CYFLD_PRT_DATAREG__OFFSET 0x00000000u
#define CYFLD_PRT_DATAREG__SIZE 0x00000008u
#define CYREG_PRT0_PS 0x40040004u
#define CYFLD_PRT_PINSTATE__OFFSET 0x00000000u
#define CYFLD_PRT_PINSTATE__SIZE 0x00000008u
#define CYFLD_PRT_PINSTATE_FLT__OFFSET 0x00000008u
#define CYFLD_PRT_PINSTATE_FLT__SIZE 0x00000001u
#define CYREG_PRT0_PC 0x40040008u
#define CYFLD_PRT_DM__OFFSET 0x00000000u
#define CYFLD_PRT_DM__SIZE 0x00000018u
#define CYVAL_PRT_DM_OFF 0x00000000u
#define CYVAL_PRT_DM_INPUT 0x00000001u
#define CYVAL_PRT_DM_0_PU 0x00000002u
#define CYVAL_PRT_DM_PD_1 0x00000003u
#define CYVAL_PRT_DM_0_Z 0x00000004u
#define CYVAL_PRT_DM_Z_1 0x00000005u
#define CYVAL_PRT_DM_0_1 0x00000006u
#define CYVAL_PRT_DM_PD_PU 0x00000007u
#define CYFLD_PRT_VTRIP_SEL__OFFSET 0x00000018u
#define CYFLD_PRT_VTRIP_SEL__SIZE 0x00000001u
#define CYFLD_PRT_SLOW__OFFSET 0x00000019u
#define CYFLD_PRT_SLOW__SIZE 0x00000001u
#define CYREG_PRT0_INTCFG 0x4004000cu
#define CYFLD_PRT_INTTYPE__OFFSET 0x00000000u
#define CYFLD_PRT_INTTYPE__SIZE 0x00000010u
#define CYVAL_PRT_INTTYPE_DISABLE 0x00000000u
#define CYVAL_PRT_INTTYPE_RISING 0x00000001u
#define CYVAL_PRT_INTTYPE_FALLING 0x00000002u
#define CYVAL_PRT_INTTYPE_BOTH 0x00000003u
#define CYFLD_PRT_INTTYPE_FLT__OFFSET 0x00000010u
#define CYFLD_PRT_INTTYPE_FLT__SIZE 0x00000002u
#define CYVAL_PRT_INTTYPE_FLT_DISABLE 0x00000000u
#define CYVAL_PRT_INTTYPE_FLT_RISING 0x00000001u
#define CYVAL_PRT_INTTYPE_FLT_FALLING 0x00000002u
#define CYVAL_PRT_INTTYPE_FLT_BOTH 0x00000003u
#define CYFLD_PRT_FLT_SELECT__OFFSET 0x00000012u
#define CYFLD_PRT_FLT_SELECT__SIZE 0x00000003u
#define CYREG_PRT0_INTSTAT 0x40040010u
#define CYFLD_PRT_INTSTAT__OFFSET 0x00000000u
#define CYFLD_PRT_INTSTAT__SIZE 0x00000008u
#define CYFLD_PRT_INTSTAT_FLT__OFFSET 0x00000008u
#define CYFLD_PRT_INTSTAT_FLT__SIZE 0x00000001u
#define CYFLD_PRT_PS__OFFSET 0x00000010u
#define CYFLD_PRT_PS__SIZE 0x00000008u
#define CYFLD_PRT_PS_FLT__OFFSET 0x00000018u
#define CYFLD_PRT_PS_FLT__SIZE 0x00000001u
#define CYREG_PRT0_PC2 0x40040018u
#define CYFLD_PRT_INP_DIS__OFFSET 0x00000000u
#define CYFLD_PRT_INP_DIS__SIZE 0x00000008u
#define CYDEV_PRT1_BASE 0x40040100u
#define CYDEV_PRT1_SIZE 0x00000100u
#define CYREG_PRT1_DR 0x40040100u
#define CYREG_PRT1_PS 0x40040104u
#define CYREG_PRT1_PC 0x40040108u
#define CYREG_PRT1_INTCFG 0x4004010cu
#define CYREG_PRT1_INTSTAT 0x40040110u
#define CYREG_PRT1_PC2 0x40040118u
#define CYDEV_PRT2_BASE 0x40040200u
#define CYDEV_PRT2_SIZE 0x00000100u
#define CYREG_PRT2_DR 0x40040200u
#define CYREG_PRT2_PS 0x40040204u
#define CYREG_PRT2_PC 0x40040208u
#define CYREG_PRT2_INTCFG 0x4004020cu
#define CYREG_PRT2_INTSTAT 0x40040210u
#define CYREG_PRT2_PC2 0x40040218u
#define CYDEV_PRT3_BASE 0x40040300u
#define CYDEV_PRT3_SIZE 0x00000100u
#define CYREG_PRT3_DR 0x40040300u
#define CYREG_PRT3_PS 0x40040304u
#define CYREG_PRT3_PC 0x40040308u
#define CYREG_PRT3_INTCFG 0x4004030cu
#define CYREG_PRT3_INTSTAT 0x40040310u
#define CYREG_PRT3_PC2 0x40040318u
#define CYDEV_PRT4_BASE 0x40040400u
#define CYDEV_PRT4_SIZE 0x00000100u
#define CYREG_PRT4_DR 0x40040400u
#define CYREG_PRT4_PS 0x40040404u
#define CYREG_PRT4_PC 0x40040408u
#define CYREG_PRT4_INTCFG 0x4004040cu
#define CYREG_PRT4_INTSTAT 0x40040410u
#define CYREG_PRT4_PC2 0x40040418u
#define CYDEV_TCPWM_BASE 0x40050000u
#define CYDEV_TCPWM_SIZE 0x00001000u
#define CYREG_TCPWM_CTRL 0x40050000u
#define CYFLD_TCPWM_COUNTER_ENABLED__OFFSET 0x00000000u
#define CYFLD_TCPWM_COUNTER_ENABLED__SIZE 0x00000008u
#define CYREG_TCPWM_CMD 0x40050008u
#define CYFLD_TCPWM_COUNTER_CAPTURE__OFFSET 0x00000000u
#define CYFLD_TCPWM_COUNTER_CAPTURE__SIZE 0x00000008u
#define CYFLD_TCPWM_COUNTER_RELOAD__OFFSET 0x00000008u
#define CYFLD_TCPWM_COUNTER_RELOAD__SIZE 0x00000008u
#define CYFLD_TCPWM_COUNTER_STOP__OFFSET 0x00000010u
#define CYFLD_TCPWM_COUNTER_STOP__SIZE 0x00000008u
#define CYFLD_TCPWM_COUNTER_START__OFFSET 0x00000018u
#define CYFLD_TCPWM_COUNTER_START__SIZE 0x00000008u
#define CYREG_TCPWM_INTR_CAUSE 0x4005000cu
#define CYFLD_TCPWM_COUNTER_INT__OFFSET 0x00000000u
#define CYFLD_TCPWM_COUNTER_INT__SIZE 0x00000008u
#define CYDEV_TCPWM_CNT0_BASE 0x40050100u
#define CYDEV_TCPWM_CNT0_SIZE 0x00000040u
#define CYREG_TCPWM_CNT0_CTRL 0x40050100u
#define CYFLD_TCPWM_CNT_AUTO_RELOAD_CC__OFFSET 0x00000000u
#define CYFLD_TCPWM_CNT_AUTO_RELOAD_CC__SIZE 0x00000001u
#define CYFLD_TCPWM_CNT_AUTO_RELOAD_PERIOD__OFFSET 0x00000001u
#define CYFLD_TCPWM_CNT_AUTO_RELOAD_PERIOD__SIZE 0x00000001u
#define CYFLD_TCPWM_CNT_PWM_SYNC_KILL__OFFSET 0x00000002u
#define CYFLD_TCPWM_CNT_PWM_SYNC_KILL__SIZE 0x00000001u
#define CYFLD_TCPWM_CNT_PWM_STOP_ON_KILL__OFFSET 0x00000003u
#define CYFLD_TCPWM_CNT_PWM_STOP_ON_KILL__SIZE 0x00000001u
#define CYFLD_TCPWM_CNT_GENERIC__OFFSET 0x00000008u
#define CYFLD_TCPWM_CNT_GENERIC__SIZE 0x00000008u
#define CYVAL_TCPWM_CNT_GENERIC_DIVBY1 0x00000000u
#define CYVAL_TCPWM_CNT_GENERIC_DIVBY2 0x00000001u
#define CYVAL_TCPWM_CNT_GENERIC_DIVBY4 0x00000002u
#define CYVAL_TCPWM_CNT_GENERIC_DIVBY8 0x00000003u
#define CYVAL_TCPWM_CNT_GENERIC_DIVBY16 0x00000004u
#define CYVAL_TCPWM_CNT_GENERIC_DIVBY32 0x00000005u
#define CYVAL_TCPWM_CNT_GENERIC_DIVBY64 0x00000006u
#define CYVAL_TCPWM_CNT_GENERIC_DIVBY128 0x00000007u
#define CYFLD_TCPWM_CNT_UP_DOWN_MODE__OFFSET 0x00000010u
#define CYFLD_TCPWM_CNT_UP_DOWN_MODE__SIZE 0x00000002u
#define CYVAL_TCPWM_CNT_UP_DOWN_MODE_COUNT_UP 0x00000000u
#define CYVAL_TCPWM_CNT_UP_DOWN_MODE_COUNT_DOWN 0x00000001u
#define CYVAL_TCPWM_CNT_UP_DOWN_MODE_COUNT_UPDN1 0x00000002u
#define CYVAL_TCPWM_CNT_UP_DOWN_MODE_COUNT_UPDN2 0x00000003u
#define CYFLD_TCPWM_CNT_ONE_SHOT__OFFSET 0x00000012u
#define CYFLD_TCPWM_CNT_ONE_SHOT__SIZE 0x00000001u
#define CYFLD_TCPWM_CNT_QUADRATURE_MODE__OFFSET 0x00000014u
#define CYFLD_TCPWM_CNT_QUADRATURE_MODE__SIZE 0x00000002u
#define CYVAL_TCPWM_CNT_QUADRATURE_MODE_X1 0x00000000u
#define CYVAL_TCPWM_CNT_QUADRATURE_MODE_X2 0x00000001u
#define CYVAL_TCPWM_CNT_QUADRATURE_MODE_X4 0x00000002u
#define CYVAL_TCPWM_CNT_QUADRATURE_MODE_INV_OUT 0x00000001u
#define CYVAL_TCPWM_CNT_QUADRATURE_MODE_INV_COMPL_OUT 0x00000002u
#define CYFLD_TCPWM_CNT_MODE__OFFSET 0x00000018u
#define CYFLD_TCPWM_CNT_MODE__SIZE 0x00000003u
#define CYVAL_TCPWM_CNT_MODE_TIMER 0x00000000u
#define CYVAL_TCPWM_CNT_MODE_CAPTURE 0x00000002u
#define CYVAL_TCPWM_CNT_MODE_QUAD 0x00000003u
#define CYVAL_TCPWM_CNT_MODE_PWM 0x00000004u
#define CYVAL_TCPWM_CNT_MODE_PWM_DT 0x00000005u
#define CYVAL_TCPWM_CNT_MODE_PWM_PR 0x00000006u
#define CYREG_TCPWM_CNT0_STATUS 0x40050104u
#define CYFLD_TCPWM_CNT_DOWN__OFFSET 0x00000000u
#define CYFLD_TCPWM_CNT_DOWN__SIZE 0x00000001u
#define CYFLD_TCPWM_CNT_RUNNING__OFFSET 0x0000001fu
#define CYFLD_TCPWM_CNT_RUNNING__SIZE 0x00000001u
#define CYREG_TCPWM_CNT0_COUNTER 0x40050108u
#define CYFLD_TCPWM_CNT_COUNTER__OFFSET 0x00000000u
#define CYFLD_TCPWM_CNT_COUNTER__SIZE 0x00000010u
#define CYREG_TCPWM_CNT0_CC 0x4005010cu
#define CYFLD_TCPWM_CNT_CC__OFFSET 0x00000000u
#define CYFLD_TCPWM_CNT_CC__SIZE 0x00000010u
#define CYREG_TCPWM_CNT0_CC_BUFF 0x40050110u
#define CYREG_TCPWM_CNT0_PERIOD 0x40050114u
#define CYFLD_TCPWM_CNT_PERIOD__OFFSET 0x00000000u
#define CYFLD_TCPWM_CNT_PERIOD__SIZE 0x00000010u
#define CYREG_TCPWM_CNT0_PERIOD_BUFF 0x40050118u
#define CYREG_TCPWM_CNT0_TR_CTRL0 0x40050120u
#define CYFLD_TCPWM_CNT_CAPTURE_SEL__OFFSET 0x00000000u
#define CYFLD_TCPWM_CNT_CAPTURE_SEL__SIZE 0x00000004u
#define CYFLD_TCPWM_CNT_COUNT_SEL__OFFSET 0x00000004u
#define CYFLD_TCPWM_CNT_COUNT_SEL__SIZE 0x00000004u
#define CYFLD_TCPWM_CNT_RELOAD_SEL__OFFSET 0x00000008u
#define CYFLD_TCPWM_CNT_RELOAD_SEL__SIZE 0x00000004u
#define CYFLD_TCPWM_CNT_STOP_SEL__OFFSET 0x0000000cu
#define CYFLD_TCPWM_CNT_STOP_SEL__SIZE 0x00000004u
#define CYFLD_TCPWM_CNT_START_SEL__OFFSET 0x00000010u
#define CYFLD_TCPWM_CNT_START_SEL__SIZE 0x00000004u
#define CYREG_TCPWM_CNT0_TR_CTRL1 0x40050124u
#define CYFLD_TCPWM_CNT_CAPTURE_EDGE__OFFSET 0x00000000u
#define CYFLD_TCPWM_CNT_CAPTURE_EDGE__SIZE 0x00000002u
#define CYVAL_TCPWM_CNT_CAPTURE_EDGE_RISING_EDGE 0x00000000u
#define CYVAL_TCPWM_CNT_CAPTURE_EDGE_FALLING_EDGE 0x00000001u
#define CYVAL_TCPWM_CNT_CAPTURE_EDGE_BOTH_EDGES 0x00000002u
#define CYVAL_TCPWM_CNT_CAPTURE_EDGE_NO_EDGE_DET 0x00000003u
#define CYFLD_TCPWM_CNT_COUNT_EDGE__OFFSET 0x00000002u
#define CYFLD_TCPWM_CNT_COUNT_EDGE__SIZE 0x00000002u
#define CYVAL_TCPWM_CNT_COUNT_EDGE_RISING_EDGE 0x00000000u
#define CYVAL_TCPWM_CNT_COUNT_EDGE_FALLING_EDGE 0x00000001u
#define CYVAL_TCPWM_CNT_COUNT_EDGE_BOTH_EDGES 0x00000002u
#define CYVAL_TCPWM_CNT_COUNT_EDGE_NO_EDGE_DET 0x00000003u
#define CYFLD_TCPWM_CNT_RELOAD_EDGE__OFFSET 0x00000004u
#define CYFLD_TCPWM_CNT_RELOAD_EDGE__SIZE 0x00000002u
#define CYVAL_TCPWM_CNT_RELOAD_EDGE_RISING_EDGE 0x00000000u
#define CYVAL_TCPWM_CNT_RELOAD_EDGE_FALLING_EDGE 0x00000001u
#define CYVAL_TCPWM_CNT_RELOAD_EDGE_BOTH_EDGES 0x00000002u
#define CYVAL_TCPWM_CNT_RELOAD_EDGE_NO_EDGE_DET 0x00000003u
#define CYFLD_TCPWM_CNT_STOP_EDGE__OFFSET 0x00000006u
#define CYFLD_TCPWM_CNT_STOP_EDGE__SIZE 0x00000002u
#define CYVAL_TCPWM_CNT_STOP_EDGE_RISING_EDGE 0x00000000u
#define CYVAL_TCPWM_CNT_STOP_EDGE_FALLING_EDGE 0x00000001u
#define CYVAL_TCPWM_CNT_STOP_EDGE_BOTH_EDGES 0x00000002u
#define CYVAL_TCPWM_CNT_STOP_EDGE_NO_EDGE_DET 0x00000003u
#define CYFLD_TCPWM_CNT_START_EDGE__OFFSET 0x00000008u
#define CYFLD_TCPWM_CNT_START_EDGE__SIZE 0x00000002u
#define CYVAL_TCPWM_CNT_START_EDGE_RISING_EDGE 0x00000000u
#define CYVAL_TCPWM_CNT_START_EDGE_FALLING_EDGE 0x00000001u
#define CYVAL_TCPWM_CNT_START_EDGE_BOTH_EDGES 0x00000002u
#define CYVAL_TCPWM_CNT_START_EDGE_NO_EDGE_DET 0x00000003u
#define CYREG_TCPWM_CNT0_TR_CTRL2 0x40050128u
#define CYFLD_TCPWM_CNT_CC_MATCH_MODE__OFFSET 0x00000000u
#define CYFLD_TCPWM_CNT_CC_MATCH_MODE__SIZE 0x00000002u
#define CYVAL_TCPWM_CNT_CC_MATCH_MODE_SET 0x00000000u
#define CYVAL_TCPWM_CNT_CC_MATCH_MODE_CLEAR 0x00000001u
#define CYVAL_TCPWM_CNT_CC_MATCH_MODE_INVERT 0x00000002u
#define CYVAL_TCPWM_CNT_CC_MATCH_MODE_NO_CHANGE 0x00000003u
#define CYFLD_TCPWM_CNT_OVERFLOW_MODE__OFFSET 0x00000002u
#define CYFLD_TCPWM_CNT_OVERFLOW_MODE__SIZE 0x00000002u
#define CYVAL_TCPWM_CNT_OVERFLOW_MODE_SET 0x00000000u
#define CYVAL_TCPWM_CNT_OVERFLOW_MODE_CLEAR 0x00000001u
#define CYVAL_TCPWM_CNT_OVERFLOW_MODE_INVERT 0x00000002u
#define CYVAL_TCPWM_CNT_OVERFLOW_MODE_NO_CHANGE 0x00000003u
#define CYFLD_TCPWM_CNT_UNDERFLOW_MODE__OFFSET 0x00000004u
#define CYFLD_TCPWM_CNT_UNDERFLOW_MODE__SIZE 0x00000002u
#define CYVAL_TCPWM_CNT_UNDERFLOW_MODE_SET 0x00000000u
#define CYVAL_TCPWM_CNT_UNDERFLOW_MODE_CLEAR 0x00000001u
#define CYVAL_TCPWM_CNT_UNDERFLOW_MODE_INVERT 0x00000002u
#define CYVAL_TCPWM_CNT_UNDERFLOW_MODE_NO_CHANGE 0x00000003u
#define CYREG_TCPWM_CNT0_INTR 0x40050130u
#define CYFLD_TCPWM_CNT_TC__OFFSET 0x00000000u
#define CYFLD_TCPWM_CNT_TC__SIZE 0x00000001u
#define CYFLD_TCPWM_CNT_CC_MATCH__OFFSET 0x00000001u
#define CYFLD_TCPWM_CNT_CC_MATCH__SIZE 0x00000001u
#define CYREG_TCPWM_CNT0_INTR_SET 0x40050134u
#define CYREG_TCPWM_CNT0_INTR_MASK 0x40050138u
#define CYREG_TCPWM_CNT0_INTR_MASKED 0x4005013cu
#define CYDEV_TCPWM_CNT1_BASE 0x40050140u
#define CYDEV_TCPWM_CNT1_SIZE 0x00000040u
#define CYREG_TCPWM_CNT1_CTRL 0x40050140u
#define CYREG_TCPWM_CNT1_STATUS 0x40050144u
#define CYREG_TCPWM_CNT1_COUNTER 0x40050148u
#define CYREG_TCPWM_CNT1_CC 0x4005014cu
#define CYREG_TCPWM_CNT1_CC_BUFF 0x40050150u
#define CYREG_TCPWM_CNT1_PERIOD 0x40050154u
#define CYREG_TCPWM_CNT1_PERIOD_BUFF 0x40050158u
#define CYREG_TCPWM_CNT1_TR_CTRL0 0x40050160u
#define CYREG_TCPWM_CNT1_TR_CTRL1 0x40050164u
#define CYREG_TCPWM_CNT1_TR_CTRL2 0x40050168u
#define CYREG_TCPWM_CNT1_INTR 0x40050170u
#define CYREG_TCPWM_CNT1_INTR_SET 0x40050174u
#define CYREG_TCPWM_CNT1_INTR_MASK 0x40050178u
#define CYREG_TCPWM_CNT1_INTR_MASKED 0x4005017cu
#define CYDEV_TCPWM_CNT2_BASE 0x40050180u
#define CYDEV_TCPWM_CNT2_SIZE 0x00000040u
#define CYREG_TCPWM_CNT2_CTRL 0x40050180u
#define CYREG_TCPWM_CNT2_STATUS 0x40050184u
#define CYREG_TCPWM_CNT2_COUNTER 0x40050188u
#define CYREG_TCPWM_CNT2_CC 0x4005018cu
#define CYREG_TCPWM_CNT2_CC_BUFF 0x40050190u
#define CYREG_TCPWM_CNT2_PERIOD 0x40050194u
#define CYREG_TCPWM_CNT2_PERIOD_BUFF 0x40050198u
#define CYREG_TCPWM_CNT2_TR_CTRL0 0x400501a0u
#define CYREG_TCPWM_CNT2_TR_CTRL1 0x400501a4u
#define CYREG_TCPWM_CNT2_TR_CTRL2 0x400501a8u
#define CYREG_TCPWM_CNT2_INTR 0x400501b0u
#define CYREG_TCPWM_CNT2_INTR_SET 0x400501b4u
#define CYREG_TCPWM_CNT2_INTR_MASK 0x400501b8u
#define CYREG_TCPWM_CNT2_INTR_MASKED 0x400501bcu
#define CYDEV_TCPWM_CNT3_BASE 0x400501c0u
#define CYDEV_TCPWM_CNT3_SIZE 0x00000040u
#define CYREG_TCPWM_CNT3_CTRL 0x400501c0u
#define CYREG_TCPWM_CNT3_STATUS 0x400501c4u
#define CYREG_TCPWM_CNT3_COUNTER 0x400501c8u
#define CYREG_TCPWM_CNT3_CC 0x400501ccu
#define CYREG_TCPWM_CNT3_CC_BUFF 0x400501d0u
#define CYREG_TCPWM_CNT3_PERIOD 0x400501d4u
#define CYREG_TCPWM_CNT3_PERIOD_BUFF 0x400501d8u
#define CYREG_TCPWM_CNT3_TR_CTRL0 0x400501e0u
#define CYREG_TCPWM_CNT3_TR_CTRL1 0x400501e4u
#define CYREG_TCPWM_CNT3_TR_CTRL2 0x400501e8u
#define CYREG_TCPWM_CNT3_INTR 0x400501f0u
#define CYREG_TCPWM_CNT3_INTR_SET 0x400501f4u
#define CYREG_TCPWM_CNT3_INTR_MASK 0x400501f8u
#define CYREG_TCPWM_CNT3_INTR_MASKED 0x400501fcu
#define CYDEV_SCB0_BASE 0x40060000u
#define CYDEV_SCB0_SIZE 0x00010000u
#define CYREG_SCB0_CTRL 0x40060000u
#define CYFLD_SCB_OVS__OFFSET 0x00000000u
#define CYFLD_SCB_OVS__SIZE 0x00000004u
#define CYFLD_SCB_EC_AM_MODE__OFFSET 0x00000008u
#define CYFLD_SCB_EC_AM_MODE__SIZE 0x00000001u
#define CYFLD_SCB_EC_OP_MODE__OFFSET 0x00000009u
#define CYFLD_SCB_EC_OP_MODE__SIZE 0x00000001u
#define CYFLD_SCB_EZ_MODE__OFFSET 0x0000000au
#define CYFLD_SCB_EZ_MODE__SIZE 0x00000001u
#define CYFLD_SCB_ADDR_ACCEPT__OFFSET 0x00000010u
#define CYFLD_SCB_ADDR_ACCEPT__SIZE 0x00000001u
#define CYFLD_SCB_BLOCK__OFFSET 0x00000011u
#define CYFLD_SCB_BLOCK__SIZE 0x00000001u
#define CYFLD_SCB_MODE__OFFSET 0x00000018u
#define CYFLD_SCB_MODE__SIZE 0x00000002u
#define CYVAL_SCB_MODE_I2C 0x00000000u
#define CYVAL_SCB_MODE_SPI 0x00000001u
#define CYVAL_SCB_MODE_UART 0x00000002u
#define CYFLD_SCB_ENABLED__OFFSET 0x0000001fu
#define CYFLD_SCB_ENABLED__SIZE 0x00000001u
#define CYREG_SCB0_STATUS 0x40060004u
#define CYFLD_SCB_EC_BUSY__OFFSET 0x00000000u
#define CYFLD_SCB_EC_BUSY__SIZE 0x00000001u
#define CYREG_SCB0_SPI_CTRL 0x40060020u
#define CYFLD_SCB_CONTINUOUS__OFFSET 0x00000000u
#define CYFLD_SCB_CONTINUOUS__SIZE 0x00000001u
#define CYFLD_SCB_SELECT_PRECEDE__OFFSET 0x00000001u
#define CYFLD_SCB_SELECT_PRECEDE__SIZE 0x00000001u
#define CYFLD_SCB_CPHA__OFFSET 0x00000002u
#define CYFLD_SCB_CPHA__SIZE 0x00000001u
#define CYFLD_SCB_CPOL__OFFSET 0x00000003u
#define CYFLD_SCB_CPOL__SIZE 0x00000001u
#define CYFLD_SCB_LATE_MISO_SAMPLE__OFFSET 0x00000004u
#define CYFLD_SCB_LATE_MISO_SAMPLE__SIZE 0x00000001u
#define CYFLD_SCB_LOOPBACK__OFFSET 0x00000010u
#define CYFLD_SCB_LOOPBACK__SIZE 0x00000001u
#define CYFLD_SCB_SLAVE_SELECT__OFFSET 0x0000001au
#define CYFLD_SCB_SLAVE_SELECT__SIZE 0x00000002u
#define CYFLD_SCB_MASTER_MODE__OFFSET 0x0000001fu
#define CYFLD_SCB_MASTER_MODE__SIZE 0x00000001u
#define CYREG_SCB0_SPI_STATUS 0x40060024u
#define CYFLD_SCB_BUS_BUSY__OFFSET 0x00000000u
#define CYFLD_SCB_BUS_BUSY__SIZE 0x00000001u
#define CYFLD_SCB_EZ_ADDR__OFFSET 0x00000008u
#define CYFLD_SCB_EZ_ADDR__SIZE 0x00000008u
#define CYREG_SCB0_UART_CTRL 0x40060040u
#define CYREG_SCB0_UART_TX_CTRL 0x40060044u
#define CYFLD_SCB_STOP_BITS__OFFSET 0x00000000u
#define CYFLD_SCB_STOP_BITS__SIZE 0x00000003u
#define CYFLD_SCB_PARITY__OFFSET 0x00000004u
#define CYFLD_SCB_PARITY__SIZE 0x00000001u
#define CYFLD_SCB_PARITY_ENABLED__OFFSET 0x00000005u
#define CYFLD_SCB_PARITY_ENABLED__SIZE 0x00000001u
#define CYFLD_SCB_RETRY_ON_NACK__OFFSET 0x00000008u
#define CYFLD_SCB_RETRY_ON_NACK__SIZE 0x00000001u
#define CYREG_SCB0_UART_RX_CTRL 0x40060048u
#define CYFLD_SCB_POLARITY__OFFSET 0x00000006u
#define CYFLD_SCB_POLARITY__SIZE 0x00000001u
#define CYFLD_SCB_DROP_ON_PARITY_ERROR__OFFSET 0x00000008u
#define CYFLD_SCB_DROP_ON_PARITY_ERROR__SIZE 0x00000001u
#define CYFLD_SCB_DROP_ON_FRAME_ERROR__OFFSET 0x00000009u
#define CYFLD_SCB_DROP_ON_FRAME_ERROR__SIZE 0x00000001u
#define CYFLD_SCB_MP_MODE__OFFSET 0x0000000au
#define CYFLD_SCB_MP_MODE__SIZE 0x00000001u
#define CYFLD_SCB_LIN_MODE__OFFSET 0x0000000cu
#define CYFLD_SCB_LIN_MODE__SIZE 0x00000001u
#define CYFLD_SCB_SKIP_START__OFFSET 0x0000000du
#define CYFLD_SCB_SKIP_START__SIZE 0x00000001u
#define CYFLD_SCB_BREAK_WIDTH__OFFSET 0x00000010u
#define CYFLD_SCB_BREAK_WIDTH__SIZE 0x00000004u
#define CYREG_SCB0_UART_RX_STATUS 0x4006004cu
#define CYFLD_SCB_BR_COUNTER__OFFSET 0x00000000u
#define CYFLD_SCB_BR_COUNTER__SIZE 0x0000000cu
#define CYREG_SCB0_I2C_CTRL 0x40060060u
#define CYFLD_SCB_HIGH_PHASE_OVS__OFFSET 0x00000000u
#define CYFLD_SCB_HIGH_PHASE_OVS__SIZE 0x00000004u
#define CYFLD_SCB_LOW_PHASE_OVS__OFFSET 0x00000004u
#define CYFLD_SCB_LOW_PHASE_OVS__SIZE 0x00000004u
#define CYFLD_SCB_M_READY_DATA_ACK__OFFSET 0x00000008u
#define CYFLD_SCB_M_READY_DATA_ACK__SIZE 0x00000001u
#define CYFLD_SCB_M_NOT_READY_DATA_NACK__OFFSET 0x00000009u
#define CYFLD_SCB_M_NOT_READY_DATA_NACK__SIZE 0x00000001u
#define CYFLD_SCB_S_GENERAL_IGNORE__OFFSET 0x0000000bu
#define CYFLD_SCB_S_GENERAL_IGNORE__SIZE 0x00000001u
#define CYFLD_SCB_S_READY_ADDR_ACK__OFFSET 0x0000000cu
#define CYFLD_SCB_S_READY_ADDR_ACK__SIZE 0x00000001u
#define CYFLD_SCB_S_READY_DATA_ACK__OFFSET 0x0000000du
#define CYFLD_SCB_S_READY_DATA_ACK__SIZE 0x00000001u
#define CYFLD_SCB_S_NOT_READY_ADDR_NACK__OFFSET 0x0000000eu
#define CYFLD_SCB_S_NOT_READY_ADDR_NACK__SIZE 0x00000001u
#define CYFLD_SCB_S_NOT_READY_DATA_NACK__OFFSET 0x0000000fu
#define CYFLD_SCB_S_NOT_READY_DATA_NACK__SIZE 0x00000001u
#define CYFLD_SCB_SLAVE_MODE__OFFSET 0x0000001eu
#define CYFLD_SCB_SLAVE_MODE__SIZE 0x00000001u
#define CYREG_SCB0_I2C_STATUS 0x40060064u
#define CYFLD_SCB_S_READ__OFFSET 0x00000004u
#define CYFLD_SCB_S_READ__SIZE 0x00000001u
#define CYFLD_SCB_M_READ__OFFSET 0x00000005u
#define CYFLD_SCB_M_READ__SIZE 0x00000001u
#define CYREG_SCB0_I2C_M_CMD 0x40060068u
#define CYFLD_SCB_M_START__OFFSET 0x00000000u
#define CYFLD_SCB_M_START__SIZE 0x00000001u
#define CYFLD_SCB_M_START_ON_IDLE__OFFSET 0x00000001u
#define CYFLD_SCB_M_START_ON_IDLE__SIZE 0x00000001u
#define CYFLD_SCB_M_ACK__OFFSET 0x00000002u
#define CYFLD_SCB_M_ACK__SIZE 0x00000001u
#define CYFLD_SCB_M_NACK__OFFSET 0x00000003u
#define CYFLD_SCB_M_NACK__SIZE 0x00000001u
#define CYFLD_SCB_M_STOP__OFFSET 0x00000004u
#define CYFLD_SCB_M_STOP__SIZE 0x00000001u
#define CYREG_SCB0_I2C_S_CMD 0x4006006cu
#define CYFLD_SCB_S_ACK__OFFSET 0x00000000u
#define CYFLD_SCB_S_ACK__SIZE 0x00000001u
#define CYFLD_SCB_S_NACK__OFFSET 0x00000001u
#define CYFLD_SCB_S_NACK__SIZE 0x00000001u
#define CYREG_SCB0_I2C_CFG 0x40060070u
#define CYFLD_SCB_SDA_FILT_HYS__OFFSET 0x00000000u
#define CYFLD_SCB_SDA_FILT_HYS__SIZE 0x00000002u
#define CYFLD_SCB_SDA_FILT_TRIM__OFFSET 0x00000002u
#define CYFLD_SCB_SDA_FILT_TRIM__SIZE 0x00000002u
#define CYFLD_SCB_SCL_FILT_HYS__OFFSET 0x00000004u
#define CYFLD_SCB_SCL_FILT_HYS__SIZE 0x00000002u
#define CYFLD_SCB_SCL_FILT_TRIM__OFFSET 0x00000006u
#define CYFLD_SCB_SCL_FILT_TRIM__SIZE 0x00000002u
#define CYFLD_SCB_SDA_FILT_OUT_HYS__OFFSET 0x00000008u
#define CYFLD_SCB_SDA_FILT_OUT_HYS__SIZE 0x00000002u
#define CYFLD_SCB_SDA_FILT_OUT_TRIM__OFFSET 0x0000000au
#define CYFLD_SCB_SDA_FILT_OUT_TRIM__SIZE 0x00000002u
#define CYFLD_SCB_SDA_FILT_HS__OFFSET 0x00000010u
#define CYFLD_SCB_SDA_FILT_HS__SIZE 0x00000001u
#define CYFLD_SCB_SDA_FILT_ENABLED__OFFSET 0x00000011u
#define CYFLD_SCB_SDA_FILT_ENABLED__SIZE 0x00000001u
#define CYFLD_SCB_SCL_FILT_HS__OFFSET 0x00000018u
#define CYFLD_SCB_SCL_FILT_HS__SIZE 0x00000001u
#define CYFLD_SCB_SCL_FILT_ENABLED__OFFSET 0x00000019u
#define CYFLD_SCB_SCL_FILT_ENABLED__SIZE 0x00000001u
#define CYFLD_SCB_SDA_FILT_OUT_HS__OFFSET 0x0000001au
#define CYFLD_SCB_SDA_FILT_OUT_HS__SIZE 0x00000001u
#define CYFLD_SCB_SDA_FILT_OUT_ENABLED__OFFSET 0x0000001bu
#define CYFLD_SCB_SDA_FILT_OUT_ENABLED__SIZE 0x00000001u
#define CYREG_SCB0_BIST_CONTROL 0x40060100u
#define CYFLD_SCB_RAM_ADDR__OFFSET 0x00000000u
#define CYFLD_SCB_RAM_ADDR__SIZE 0x00000005u
#define CYFLD_SCB_RAM_OP1__OFFSET 0x00000010u
#define CYFLD_SCB_RAM_OP1__SIZE 0x00000002u
#define CYFLD_SCB_RAM_OP2__OFFSET 0x00000012u
#define CYFLD_SCB_RAM_OP2__SIZE 0x00000002u
#define CYFLD_SCB_RAM_OP3__OFFSET 0x00000014u
#define CYFLD_SCB_RAM_OP3__SIZE 0x00000002u
#define CYFLD_SCB_RAM_OP4__OFFSET 0x00000016u
#define CYFLD_SCB_RAM_OP4__SIZE 0x00000002u
#define CYFLD_SCB_RAM_OPCNT__OFFSET 0x00000018u
#define CYFLD_SCB_RAM_OPCNT__SIZE 0x00000002u
#define CYFLD_SCB_RAM_PREADR__OFFSET 0x0000001au
#define CYFLD_SCB_RAM_PREADR__SIZE 0x00000001u
#define CYFLD_SCB_RAM_WORD__OFFSET 0x0000001bu
#define CYFLD_SCB_RAM_WORD__SIZE 0x00000001u
#define CYFLD_SCB_RAM_FAIL__OFFSET 0x0000001cu
#define CYFLD_SCB_RAM_FAIL__SIZE 0x00000001u
#define CYFLD_SCB_RAM_GO__OFFSET 0x0000001du
#define CYFLD_SCB_RAM_GO__SIZE 0x00000001u
#define CYREG_SCB0_BIST_DATA 0x40060104u
#define CYFLD_SCB_RAM_DATA__OFFSET 0x00000000u
#define CYFLD_SCB_RAM_DATA__SIZE 0x00000010u
#define CYREG_SCB0_TX_CTRL 0x40060200u
#define CYFLD_SCB_DATA_WIDTH__OFFSET 0x00000000u
#define CYFLD_SCB_DATA_WIDTH__SIZE 0x00000004u
#define CYFLD_SCB_MSB_FIRST__OFFSET 0x00000008u
#define CYFLD_SCB_MSB_FIRST__SIZE 0x00000001u
#define CYREG_SCB0_TX_FIFO_CTRL 0x40060204u
#define CYFLD_SCB_TRIGGER_LEVEL__OFFSET 0x00000000u
#define CYFLD_SCB_TRIGGER_LEVEL__SIZE 0x00000003u
#define CYFLD_SCB_CLEAR__OFFSET 0x00000010u
#define CYFLD_SCB_CLEAR__SIZE 0x00000001u
#define CYFLD_SCB_FREEZE__OFFSET 0x00000011u
#define CYFLD_SCB_FREEZE__SIZE 0x00000001u
#define CYREG_SCB0_TX_FIFO_STATUS 0x40060208u
#define CYFLD_SCB_USED__OFFSET 0x00000000u
#define CYFLD_SCB_USED__SIZE 0x00000004u
#define CYFLD_SCB_SR_VALID__OFFSET 0x0000000fu
#define CYFLD_SCB_SR_VALID__SIZE 0x00000001u
#define CYFLD_SCB_RD_PTR__OFFSET 0x00000010u
#define CYFLD_SCB_RD_PTR__SIZE 0x00000003u
#define CYFLD_SCB_WR_PTR__OFFSET 0x00000018u
#define CYFLD_SCB_WR_PTR__SIZE 0x00000003u
#define CYREG_SCB0_TX_FIFO_WR 0x40060240u
#define CYFLD_SCB_DATA__OFFSET 0x00000000u
#define CYFLD_SCB_DATA__SIZE 0x00000010u
#define CYREG_SCB0_RX_CTRL 0x40060300u
#define CYFLD_SCB_MEDIAN__OFFSET 0x00000009u
#define CYFLD_SCB_MEDIAN__SIZE 0x00000001u
#define CYREG_SCB0_RX_FIFO_CTRL 0x40060304u
#define CYREG_SCB0_RX_FIFO_STATUS 0x40060308u
#define CYREG_SCB0_RX_MATCH 0x40060310u
#define CYFLD_SCB_ADDR__OFFSET 0x00000000u
#define CYFLD_SCB_ADDR__SIZE 0x00000008u
#define CYFLD_SCB_MASK__OFFSET 0x00000010u
#define CYFLD_SCB_MASK__SIZE 0x00000008u
#define CYREG_SCB0_RX_FIFO_RD 0x40060340u
#define CYREG_SCB0_RX_FIFO_RD_SILENT 0x40060344u
#define CYREG_SCB0_EZ_DATA00 0x40060400u
#define CYFLD_SCB_EZ_DATA__OFFSET 0x00000000u
#define CYFLD_SCB_EZ_DATA__SIZE 0x00000008u
#define CYREG_SCB0_EZ_DATA01 0x40060404u
#define CYREG_SCB0_EZ_DATA02 0x40060408u
#define CYREG_SCB0_EZ_DATA03 0x4006040cu
#define CYREG_SCB0_EZ_DATA04 0x40060410u
#define CYREG_SCB0_EZ_DATA05 0x40060414u
#define CYREG_SCB0_EZ_DATA06 0x40060418u
#define CYREG_SCB0_EZ_DATA07 0x4006041cu
#define CYREG_SCB0_EZ_DATA08 0x40060420u
#define CYREG_SCB0_EZ_DATA09 0x40060424u
#define CYREG_SCB0_EZ_DATA10 0x40060428u
#define CYREG_SCB0_EZ_DATA11 0x4006042cu
#define CYREG_SCB0_EZ_DATA12 0x40060430u
#define CYREG_SCB0_EZ_DATA13 0x40060434u
#define CYREG_SCB0_EZ_DATA14 0x40060438u
#define CYREG_SCB0_EZ_DATA15 0x4006043cu
#define CYREG_SCB0_EZ_DATA16 0x40060440u
#define CYREG_SCB0_EZ_DATA17 0x40060444u
#define CYREG_SCB0_EZ_DATA18 0x40060448u
#define CYREG_SCB0_EZ_DATA19 0x4006044cu
#define CYREG_SCB0_EZ_DATA20 0x40060450u
#define CYREG_SCB0_EZ_DATA21 0x40060454u
#define CYREG_SCB0_EZ_DATA22 0x40060458u
#define CYREG_SCB0_EZ_DATA23 0x4006045cu
#define CYREG_SCB0_EZ_DATA24 0x40060460u
#define CYREG_SCB0_EZ_DATA25 0x40060464u
#define CYREG_SCB0_EZ_DATA26 0x40060468u
#define CYREG_SCB0_EZ_DATA27 0x4006046cu
#define CYREG_SCB0_EZ_DATA28 0x40060470u
#define CYREG_SCB0_EZ_DATA29 0x40060474u
#define CYREG_SCB0_EZ_DATA30 0x40060478u
#define CYREG_SCB0_EZ_DATA31 0x4006047cu
#define CYREG_SCB0_INTR_CAUSE 0x40060e00u
#define CYFLD_SCB_M__OFFSET 0x00000000u
#define CYFLD_SCB_M__SIZE 0x00000001u
#define CYFLD_SCB_S__OFFSET 0x00000001u
#define CYFLD_SCB_S__SIZE 0x00000001u
#define CYFLD_SCB_TX__OFFSET 0x00000002u
#define CYFLD_SCB_TX__SIZE 0x00000001u
#define CYFLD_SCB_RX__OFFSET 0x00000003u
#define CYFLD_SCB_RX__SIZE 0x00000001u
#define CYFLD_SCB_I2C_EC__OFFSET 0x00000004u
#define CYFLD_SCB_I2C_EC__SIZE 0x00000001u
#define CYFLD_SCB_SPI_EC__OFFSET 0x00000005u
#define CYFLD_SCB_SPI_EC__SIZE 0x00000001u
#define CYREG_SCB0_INTR_I2C_EC 0x40060e80u
#define CYFLD_SCB_WAKE_UP__OFFSET 0x00000000u
#define CYFLD_SCB_WAKE_UP__SIZE 0x00000001u
#define CYFLD_SCB_EZ_STOP__OFFSET 0x00000001u
#define CYFLD_SCB_EZ_STOP__SIZE 0x00000001u
#define CYFLD_SCB_EZ_WRITE_STOP__OFFSET 0x00000002u
#define CYFLD_SCB_EZ_WRITE_STOP__SIZE 0x00000001u
#define CYREG_SCB0_INTR_I2C_EC_MASK 0x40060e88u
#define CYREG_SCB0_INTR_I2C_EC_MASKED 0x40060e8cu
#define CYREG_SCB0_INTR_SPI_EC 0x40060ec0u
#define CYREG_SCB0_INTR_SPI_EC_MASK 0x40060ec8u
#define CYREG_SCB0_INTR_SPI_EC_MASKED 0x40060eccu
#define CYREG_SCB0_INTR_M 0x40060f00u
#define CYFLD_SCB_I2C_ARB_LOST__OFFSET 0x00000000u
#define CYFLD_SCB_I2C_ARB_LOST__SIZE 0x00000001u
#define CYFLD_SCB_I2C_NACK__OFFSET 0x00000001u
#define CYFLD_SCB_I2C_NACK__SIZE 0x00000001u
#define CYFLD_SCB_I2C_ACK__OFFSET 0x00000002u
#define CYFLD_SCB_I2C_ACK__SIZE 0x00000001u
#define CYFLD_SCB_I2C_STOP__OFFSET 0x00000004u
#define CYFLD_SCB_I2C_STOP__SIZE 0x00000001u
#define CYFLD_SCB_I2C_BUS_ERROR__OFFSET 0x00000008u
#define CYFLD_SCB_I2C_BUS_ERROR__SIZE 0x00000001u
#define CYFLD_SCB_SPI_DONE__OFFSET 0x00000009u
#define CYFLD_SCB_SPI_DONE__SIZE 0x00000001u
#define CYREG_SCB0_INTR_M_SET 0x40060f04u
#define CYREG_SCB0_INTR_M_MASK 0x40060f08u
#define CYREG_SCB0_INTR_M_MASKED 0x40060f0cu
#define CYREG_SCB0_INTR_S 0x40060f40u
#define CYFLD_SCB_I2C_WRITE_STOP__OFFSET 0x00000003u
#define CYFLD_SCB_I2C_WRITE_STOP__SIZE 0x00000001u
#define CYFLD_SCB_I2C_START__OFFSET 0x00000005u
#define CYFLD_SCB_I2C_START__SIZE 0x00000001u
#define CYFLD_SCB_I2C_ADDR_MATCH__OFFSET 0x00000006u
#define CYFLD_SCB_I2C_ADDR_MATCH__SIZE 0x00000001u
#define CYFLD_SCB_I2C_GENERAL__OFFSET 0x00000007u
#define CYFLD_SCB_I2C_GENERAL__SIZE 0x00000001u
#define CYFLD_SCB_SPI_EZ_WRITE_STOP__OFFSET 0x00000009u
#define CYFLD_SCB_SPI_EZ_WRITE_STOP__SIZE 0x00000001u
#define CYFLD_SCB_SPI_EZ_STOP__OFFSET 0x0000000au
#define CYFLD_SCB_SPI_EZ_STOP__SIZE 0x00000001u
#define CYFLD_SCB_SPI_BUS_ERROR__OFFSET 0x0000000bu
#define CYFLD_SCB_SPI_BUS_ERROR__SIZE 0x00000001u
#define CYREG_SCB0_INTR_S_SET 0x40060f44u
#define CYREG_SCB0_INTR_S_MASK 0x40060f48u
#define CYREG_SCB0_INTR_S_MASKED 0x40060f4cu
#define CYREG_SCB0_INTR_TX 0x40060f80u
#define CYFLD_SCB_TRIGGER__OFFSET 0x00000000u
#define CYFLD_SCB_TRIGGER__SIZE 0x00000001u
#define CYFLD_SCB_NOT_FULL__OFFSET 0x00000001u
#define CYFLD_SCB_NOT_FULL__SIZE 0x00000001u
#define CYFLD_SCB_EMPTY__OFFSET 0x00000004u
#define CYFLD_SCB_EMPTY__SIZE 0x00000001u
#define CYFLD_SCB_OVERFLOW__OFFSET 0x00000005u
#define CYFLD_SCB_OVERFLOW__SIZE 0x00000001u
#define CYFLD_SCB_UNDERFLOW__OFFSET 0x00000006u
#define CYFLD_SCB_UNDERFLOW__SIZE 0x00000001u
#define CYFLD_SCB_BLOCKED__OFFSET 0x00000007u
#define CYFLD_SCB_BLOCKED__SIZE 0x00000001u
#define CYFLD_SCB_UART_NACK__OFFSET 0x00000008u
#define CYFLD_SCB_UART_NACK__SIZE 0x00000001u
#define CYFLD_SCB_UART_DONE__OFFSET 0x00000009u
#define CYFLD_SCB_UART_DONE__SIZE 0x00000001u
#define CYFLD_SCB_UART_ARB_LOST__OFFSET 0x0000000au
#define CYFLD_SCB_UART_ARB_LOST__SIZE 0x00000001u
#define CYREG_SCB0_INTR_TX_SET 0x40060f84u
#define CYREG_SCB0_INTR_TX_MASK 0x40060f88u
#define CYREG_SCB0_INTR_TX_MASKED 0x40060f8cu
#define CYREG_SCB0_INTR_RX 0x40060fc0u
#define CYFLD_SCB_NOT_EMPTY__OFFSET 0x00000002u
#define CYFLD_SCB_NOT_EMPTY__SIZE 0x00000001u
#define CYFLD_SCB_FULL__OFFSET 0x00000003u
#define CYFLD_SCB_FULL__SIZE 0x00000001u
#define CYFLD_SCB_FRAME_ERROR__OFFSET 0x00000008u
#define CYFLD_SCB_FRAME_ERROR__SIZE 0x00000001u
#define CYFLD_SCB_PARITY_ERROR__OFFSET 0x00000009u
#define CYFLD_SCB_PARITY_ERROR__SIZE 0x00000001u
#define CYFLD_SCB_BAUD_DETECT__OFFSET 0x0000000au
#define CYFLD_SCB_BAUD_DETECT__SIZE 0x00000001u
#define CYFLD_SCB_BREAK_DETECT__OFFSET 0x0000000bu
#define CYFLD_SCB_BREAK_DETECT__SIZE 0x00000001u
#define CYREG_SCB0_INTR_RX_SET 0x40060fc4u
#define CYREG_SCB0_INTR_RX_MASK 0x40060fc8u
#define CYREG_SCB0_INTR_RX_MASKED 0x40060fccu
#define CYDEV_SCB1_BASE 0x40070000u
#define CYDEV_SCB1_SIZE 0x00010000u
#define CYREG_SCB1_CTRL 0x40070000u
#define CYREG_SCB1_STATUS 0x40070004u
#define CYREG_SCB1_SPI_CTRL 0x40070020u
#define CYREG_SCB1_SPI_STATUS 0x40070024u
#define CYREG_SCB1_UART_CTRL 0x40070040u
#define CYREG_SCB1_UART_TX_CTRL 0x40070044u
#define CYREG_SCB1_UART_RX_CTRL 0x40070048u
#define CYREG_SCB1_UART_RX_STATUS 0x4007004cu
#define CYREG_SCB1_I2C_CTRL 0x40070060u
#define CYREG_SCB1_I2C_STATUS 0x40070064u
#define CYREG_SCB1_I2C_M_CMD 0x40070068u
#define CYREG_SCB1_I2C_S_CMD 0x4007006cu
#define CYREG_SCB1_I2C_CFG 0x40070070u
#define CYREG_SCB1_BIST_CONTROL 0x40070100u
#define CYREG_SCB1_BIST_DATA 0x40070104u
#define CYREG_SCB1_TX_CTRL 0x40070200u
#define CYREG_SCB1_TX_FIFO_CTRL 0x40070204u
#define CYREG_SCB1_TX_FIFO_STATUS 0x40070208u
#define CYREG_SCB1_TX_FIFO_WR 0x40070240u
#define CYREG_SCB1_RX_CTRL 0x40070300u
#define CYREG_SCB1_RX_FIFO_CTRL 0x40070304u
#define CYREG_SCB1_RX_FIFO_STATUS 0x40070308u
#define CYREG_SCB1_RX_MATCH 0x40070310u
#define CYREG_SCB1_RX_FIFO_RD 0x40070340u
#define CYREG_SCB1_RX_FIFO_RD_SILENT 0x40070344u
#define CYREG_SCB1_EZ_DATA00 0x40070400u
#define CYREG_SCB1_EZ_DATA01 0x40070404u
#define CYREG_SCB1_EZ_DATA02 0x40070408u
#define CYREG_SCB1_EZ_DATA03 0x4007040cu
#define CYREG_SCB1_EZ_DATA04 0x40070410u
#define CYREG_SCB1_EZ_DATA05 0x40070414u
#define CYREG_SCB1_EZ_DATA06 0x40070418u
#define CYREG_SCB1_EZ_DATA07 0x4007041cu
#define CYREG_SCB1_EZ_DATA08 0x40070420u
#define CYREG_SCB1_EZ_DATA09 0x40070424u
#define CYREG_SCB1_EZ_DATA10 0x40070428u
#define CYREG_SCB1_EZ_DATA11 0x4007042cu
#define CYREG_SCB1_EZ_DATA12 0x40070430u
#define CYREG_SCB1_EZ_DATA13 0x40070434u
#define CYREG_SCB1_EZ_DATA14 0x40070438u
#define CYREG_SCB1_EZ_DATA15 0x4007043cu
#define CYREG_SCB1_EZ_DATA16 0x40070440u
#define CYREG_SCB1_EZ_DATA17 0x40070444u
#define CYREG_SCB1_EZ_DATA18 0x40070448u
#define CYREG_SCB1_EZ_DATA19 0x4007044cu
#define CYREG_SCB1_EZ_DATA20 0x40070450u
#define CYREG_SCB1_EZ_DATA21 0x40070454u
#define CYREG_SCB1_EZ_DATA22 0x40070458u
#define CYREG_SCB1_EZ_DATA23 0x4007045cu
#define CYREG_SCB1_EZ_DATA24 0x40070460u
#define CYREG_SCB1_EZ_DATA25 0x40070464u
#define CYREG_SCB1_EZ_DATA26 0x40070468u
#define CYREG_SCB1_EZ_DATA27 0x4007046cu
#define CYREG_SCB1_EZ_DATA28 0x40070470u
#define CYREG_SCB1_EZ_DATA29 0x40070474u
#define CYREG_SCB1_EZ_DATA30 0x40070478u
#define CYREG_SCB1_EZ_DATA31 0x4007047cu
#define CYREG_SCB1_INTR_CAUSE 0x40070e00u
#define CYREG_SCB1_INTR_I2C_EC 0x40070e80u
#define CYREG_SCB1_INTR_I2C_EC_MASK 0x40070e88u
#define CYREG_SCB1_INTR_I2C_EC_MASKED 0x40070e8cu
#define CYREG_SCB1_INTR_SPI_EC 0x40070ec0u
#define CYREG_SCB1_INTR_SPI_EC_MASK 0x40070ec8u
#define CYREG_SCB1_INTR_SPI_EC_MASKED 0x40070eccu
#define CYREG_SCB1_INTR_M 0x40070f00u
#define CYREG_SCB1_INTR_M_SET 0x40070f04u
#define CYREG_SCB1_INTR_M_MASK 0x40070f08u
#define CYREG_SCB1_INTR_M_MASKED 0x40070f0cu
#define CYREG_SCB1_INTR_S 0x40070f40u
#define CYREG_SCB1_INTR_S_SET 0x40070f44u
#define CYREG_SCB1_INTR_S_MASK 0x40070f48u
#define CYREG_SCB1_INTR_S_MASKED 0x40070f4cu
#define CYREG_SCB1_INTR_TX 0x40070f80u
#define CYREG_SCB1_INTR_TX_SET 0x40070f84u
#define CYREG_SCB1_INTR_TX_MASK 0x40070f88u
#define CYREG_SCB1_INTR_TX_MASKED 0x40070f8cu
#define CYREG_SCB1_INTR_RX 0x40070fc0u
#define CYREG_SCB1_INTR_RX_SET 0x40070fc4u
#define CYREG_SCB1_INTR_RX_MASK 0x40070fc8u
#define CYREG_SCB1_INTR_RX_MASKED 0x40070fccu
#define CYDEV_CSD_BASE 0x40080000u
#define CYDEV_CSD_SIZE 0x00010000u
#define CYREG_CSD_ID 0x40080000u
#define CYFLD_CSD_ID__OFFSET 0x00000000u
#define CYFLD_CSD_ID__SIZE 0x00000010u
#define CYFLD_CSD_REVISION__OFFSET 0x00000010u
#define CYFLD_CSD_REVISION__SIZE 0x00000010u
#define CYREG_CSD_CONFIG 0x40080004u
#define CYFLD_CSD_DSI_SAMPLE_EN__OFFSET 0x00000000u
#define CYFLD_CSD_DSI_SAMPLE_EN__SIZE 0x00000001u
#define CYFLD_CSD_SAMPLE_SYNC__OFFSET 0x00000001u
#define CYFLD_CSD_SAMPLE_SYNC__SIZE 0x00000001u
#define CYFLD_CSD_PRS_CLEAR__OFFSET 0x00000005u
#define CYFLD_CSD_PRS_CLEAR__SIZE 0x00000001u
#define CYFLD_CSD_PRS_SELECT__OFFSET 0x00000006u
#define CYFLD_CSD_PRS_SELECT__SIZE 0x00000001u
#define CYVAL_CSD_PRS_SELECT_DIV2 0x00000000u
#define CYVAL_CSD_PRS_SELECT_PRS 0x00000001u
#define CYFLD_CSD_PRS_12_8__OFFSET 0x00000007u
#define CYFLD_CSD_PRS_12_8__SIZE 0x00000001u
#define CYVAL_CSD_PRS_12_8_8B 0x00000000u
#define CYVAL_CSD_PRS_12_8_12B 0x00000001u
#define CYFLD_CSD_DSI_SENSE_EN__OFFSET 0x00000008u
#define CYFLD_CSD_DSI_SENSE_EN__SIZE 0x00000001u
#define CYFLD_CSD_SHIELD_DELAY__OFFSET 0x00000009u
#define CYFLD_CSD_SHIELD_DELAY__SIZE 0x00000002u
#define CYFLD_CSD_SENSE_COMP_BW__OFFSET 0x0000000bu
#define CYFLD_CSD_SENSE_COMP_BW__SIZE 0x00000001u
#define CYVAL_CSD_SENSE_COMP_BW_LOW 0x00000000u
#define CYVAL_CSD_SENSE_COMP_BW_HIGH 0x00000001u
#define CYFLD_CSD_SENSE_EN__OFFSET 0x0000000cu
#define CYFLD_CSD_SENSE_EN__SIZE 0x00000001u
#define CYFLD_CSD_REFBUF_EN__OFFSET 0x0000000du
#define CYFLD_CSD_REFBUF_EN__SIZE 0x00000001u
#define CYFLD_CSD_COMP_MODE__OFFSET 0x0000000eu
#define CYFLD_CSD_COMP_MODE__SIZE 0x00000001u
#define CYVAL_CSD_COMP_MODE_CHARGE_BUF 0x00000000u
#define CYVAL_CSD_COMP_MODE_CHARGE_IO 0x00000001u
#define CYFLD_CSD_COMP_PIN__OFFSET 0x0000000fu
#define CYFLD_CSD_COMP_PIN__SIZE 0x00000001u
#define CYVAL_CSD_COMP_PIN_CHANNEL1 0x00000000u
#define CYVAL_CSD_COMP_PIN_CHANNEL2 0x00000001u
#define CYFLD_CSD_POLARITY__OFFSET 0x00000010u
#define CYFLD_CSD_POLARITY__SIZE 0x00000001u
#define CYVAL_CSD_POLARITY_VSSIO 0x00000000u
#define CYVAL_CSD_POLARITY_VDDIO 0x00000001u
#define CYFLD_CSD_POLARITY2__OFFSET 0x00000011u
#define CYFLD_CSD_POLARITY2__SIZE 0x00000001u
#define CYVAL_CSD_POLARITY2_VSSIO 0x00000000u
#define CYVAL_CSD_POLARITY2_VDDIO 0x00000001u
#define CYFLD_CSD_MUTUAL_CAP__OFFSET 0x00000012u
#define CYFLD_CSD_MUTUAL_CAP__SIZE 0x00000001u
#define CYVAL_CSD_MUTUAL_CAP_SELFCAP 0x00000000u
#define CYVAL_CSD_MUTUAL_CAP_MUTUALCAP 0x00000001u
#define CYFLD_CSD_SENSE_COMP_EN__OFFSET 0x00000013u
#define CYFLD_CSD_SENSE_COMP_EN__SIZE 0x00000001u
#define CYFLD_CSD_REBUF_OUTSEL__OFFSET 0x00000015u
#define CYFLD_CSD_REBUF_OUTSEL__SIZE 0x00000001u
#define CYVAL_CSD_REBUF_OUTSEL_AMUXA 0x00000000u
#define CYVAL_CSD_REBUF_OUTSEL_AMUXB 0x00000001u
#define CYFLD_CSD_SENSE_INSEL__OFFSET 0x00000016u
#define CYFLD_CSD_SENSE_INSEL__SIZE 0x00000001u
#define CYVAL_CSD_SENSE_INSEL_SENSE_CHANNEL1 0x00000000u
#define CYVAL_CSD_SENSE_INSEL_SENSE_AMUXA 0x00000001u
#define CYFLD_CSD_REFBUF_DRV__OFFSET 0x00000017u
#define CYFLD_CSD_REFBUF_DRV__SIZE 0x00000002u
#define CYVAL_CSD_REFBUF_DRV_OFF 0x00000000u
#define CYVAL_CSD_REFBUF_DRV_DRV_1 0x00000001u
#define CYVAL_CSD_REFBUF_DRV_DRV_2 0x00000002u
#define CYVAL_CSD_REFBUF_DRV_DRV_3 0x00000003u
#define CYFLD_CSD_DDFTSEL__OFFSET 0x0000001au
#define CYFLD_CSD_DDFTSEL__SIZE 0x00000003u
#define CYVAL_CSD_DDFTSEL_NORMAL 0x00000000u
#define CYVAL_CSD_DDFTSEL_CSD_SENSE 0x00000001u
#define CYVAL_CSD_DDFTSEL_CSD_SHIELD 0x00000002u
#define CYVAL_CSD_DDFTSEL_CLK_SAMPLE 0x00000003u
#define CYVAL_CSD_DDFTSEL_COMP_OUT 0x00000004u
#define CYFLD_CSD_ADFTEN__OFFSET 0x0000001du
#define CYFLD_CSD_ADFTEN__SIZE 0x00000001u
#define CYFLD_CSD_DDFTCOMP__OFFSET 0x0000001eu
#define CYFLD_CSD_DDFTCOMP__SIZE 0x00000001u
#define CYVAL_CSD_DDFTCOMP_REFBUFCOMP 0x00000000u
#define CYVAL_CSD_DDFTCOMP_SENSECOMP 0x00000001u
#define CYFLD_CSD_ENABLE__OFFSET 0x0000001fu
#define CYFLD_CSD_ENABLE__SIZE 0x00000001u
#define CYREG_CSD_IDAC 0x40080008u
#define CYFLD_CSD_IDAC1__OFFSET 0x00000000u
#define CYFLD_CSD_IDAC1__SIZE 0x00000008u
#define CYFLD_CSD_IDAC1_MODE__OFFSET 0x00000008u
#define CYFLD_CSD_IDAC1_MODE__SIZE 0x00000002u
#define CYVAL_CSD_IDAC1_MODE_OFF 0x00000000u
#define CYVAL_CSD_IDAC1_MODE_FIXED 0x00000001u
#define CYVAL_CSD_IDAC1_MODE_VARIABLE 0x00000002u
#define CYVAL_CSD_IDAC1_MODE_DSI 0x00000003u
#define CYFLD_CSD_IDAC1_RANGE__OFFSET 0x0000000au
#define CYFLD_CSD_IDAC1_RANGE__SIZE 0x00000001u
#define CYVAL_CSD_IDAC1_RANGE_4X 0x00000000u
#define CYVAL_CSD_IDAC1_RANGE_8X 0x00000001u
#define CYFLD_CSD_IDAC2__OFFSET 0x00000010u
#define CYFLD_CSD_IDAC2__SIZE 0x00000007u
#define CYFLD_CSD_IDAC2_MODE__OFFSET 0x00000018u
#define CYFLD_CSD_IDAC2_MODE__SIZE 0x00000002u
#define CYVAL_CSD_IDAC2_MODE_OFF 0x00000000u
#define CYVAL_CSD_IDAC2_MODE_FIXED 0x00000001u
#define CYVAL_CSD_IDAC2_MODE_VARIABLE 0x00000002u
#define CYVAL_CSD_IDAC2_MODE_DSI 0x00000003u
#define CYFLD_CSD_IDAC2_RANGE__OFFSET 0x0000001au
#define CYFLD_CSD_IDAC2_RANGE__SIZE 0x00000001u
#define CYVAL_CSD_IDAC2_RANGE_4X 0x00000000u
#define CYVAL_CSD_IDAC2_RANGE_8X 0x00000001u
#define CYFLD_CSD_FEEDBACK_MODE__OFFSET 0x0000001eu
#define CYFLD_CSD_FEEDBACK_MODE__SIZE 0x00000001u
#define CYVAL_CSD_FEEDBACK_MODE_FLOP 0x00000000u
#define CYVAL_CSD_FEEDBACK_MODE_COMP 0x00000001u
#define CYREG_CSD_COUNTER 0x4008000cu
#define CYFLD_CSD_COUNTER__OFFSET 0x00000000u
#define CYFLD_CSD_COUNTER__SIZE 0x00000010u
#define CYFLD_CSD_PERIOD__OFFSET 0x00000010u
#define CYFLD_CSD_PERIOD__SIZE 0x00000010u
#define CYREG_CSD_STATUS 0x40080010u
#define CYFLD_CSD_CSD_CHARGE__OFFSET 0x00000000u
#define CYFLD_CSD_CSD_CHARGE__SIZE 0x00000001u
#define CYFLD_CSD_CSD_SENSE__OFFSET 0x00000001u
#define CYFLD_CSD_CSD_SENSE__SIZE 0x00000001u
#define CYFLD_CSD_COMP_OUT__OFFSET 0x00000002u
#define CYFLD_CSD_COMP_OUT__SIZE 0x00000001u
#define CYVAL_CSD_COMP_OUT_C_LT_VREF 0x00000000u
#define CYVAL_CSD_COMP_OUT_C_GT_VREF 0x00000001u
#define CYFLD_CSD_SAMPLE__OFFSET 0x00000003u
#define CYFLD_CSD_SAMPLE__SIZE 0x00000001u
#define CYREG_CSD_INTR 0x40080014u
#define CYFLD_CSD_CSD__OFFSET 0x00000000u
#define CYFLD_CSD_CSD__SIZE 0x00000001u
#define CYREG_CSD_INTR_SET 0x40080018u
#define CYREG_CSD_TRIM1 0x4008ff00u
#define CYFLD_CSD_IDAC1_SRC_TRIM__OFFSET 0x00000000u
#define CYFLD_CSD_IDAC1_SRC_TRIM__SIZE 0x00000004u
#define CYFLD_CSD_IDAC2_SRC_TRIM__OFFSET 0x00000004u
#define CYFLD_CSD_IDAC2_SRC_TRIM__SIZE 0x00000004u
#define CYREG_CSD_TRIM2 0x4008ff04u
#define CYFLD_CSD_IDAC1_SNK_TRIM__OFFSET 0x00000000u
#define CYFLD_CSD_IDAC1_SNK_TRIM__SIZE 0x00000004u
#define CYFLD_CSD_IDAC2_SNK_TRIM__OFFSET 0x00000004u
#define CYFLD_CSD_IDAC2_SNK_TRIM__SIZE 0x00000004u
#define CYDEV_LCD_BASE 0x40090000u
#define CYDEV_LCD_SIZE 0x00010000u
#define CYREG_LCD_ID 0x40090000u
#define CYFLD_LCD_ID__OFFSET 0x00000000u
#define CYFLD_LCD_ID__SIZE 0x00000010u
#define CYFLD_LCD_REVISION__OFFSET 0x00000010u
#define CYFLD_LCD_REVISION__SIZE 0x00000010u
#define CYREG_LCD_DIVIDER 0x40090004u
#define CYFLD_LCD_SUBFR_DIV__OFFSET 0x00000000u
#define CYFLD_LCD_SUBFR_DIV__SIZE 0x00000010u
#define CYFLD_LCD_DEAD_DIV__OFFSET 0x00000010u
#define CYFLD_LCD_DEAD_DIV__SIZE 0x00000010u
#define CYREG_LCD_CONTROL 0x40090008u
#define CYFLD_LCD_LS_EN__OFFSET 0x00000000u
#define CYFLD_LCD_LS_EN__SIZE 0x00000001u
#define CYFLD_LCD_HS_EN__OFFSET 0x00000001u
#define CYFLD_LCD_HS_EN__SIZE 0x00000001u
#define CYFLD_LCD_LCD_MODE__OFFSET 0x00000002u
#define CYFLD_LCD_LCD_MODE__SIZE 0x00000001u
#define CYVAL_LCD_LCD_MODE_LS 0x00000000u
#define CYVAL_LCD_LCD_MODE_HS 0x00000001u
#define CYFLD_LCD_TYPE__OFFSET 0x00000003u
#define CYFLD_LCD_TYPE__SIZE 0x00000001u
#define CYVAL_LCD_TYPE_A 0x00000000u
#define CYVAL_LCD_TYPE_B 0x00000001u
#define CYFLD_LCD_OP_MODE__OFFSET 0x00000004u
#define CYFLD_LCD_OP_MODE__SIZE 0x00000001u
#define CYVAL_LCD_OP_MODE_PWM 0x00000000u
#define CYVAL_LCD_OP_MODE_CORRELATION 0x00000001u
#define CYFLD_LCD_BIAS__OFFSET 0x00000005u
#define CYFLD_LCD_BIAS__SIZE 0x00000002u
#define CYVAL_LCD_BIAS_HALF 0x00000000u
#define CYVAL_LCD_BIAS_THIRD 0x00000001u
#define CYVAL_LCD_BIAS_FOURTH 0x00000002u
#define CYVAL_LCD_BIAS_FIFTH 0x00000003u
#define CYFLD_LCD_COM_NUM__OFFSET 0x00000008u
#define CYFLD_LCD_COM_NUM__SIZE 0x00000004u
#define CYFLD_LCD_LS_EN_STAT__OFFSET 0x0000001fu
#define CYFLD_LCD_LS_EN_STAT__SIZE 0x00000001u
#define CYREG_LCD_DATA00 0x40090100u
#define CYFLD_LCD_DATA__OFFSET 0x00000000u
#define CYFLD_LCD_DATA__SIZE 0x00000020u
#define CYREG_LCD_DATA01 0x40090104u
#define CYREG_LCD_DATA02 0x40090108u
#define CYREG_LCD_DATA03 0x4009010cu
#define CYREG_LCD_DATA04 0x40090110u
#define CYDEV_LPCOMP_BASE 0x400a0000u
#define CYDEV_LPCOMP_SIZE 0x00010000u
#define CYREG_LPCOMP_ID 0x400a0000u
#define CYFLD_LPCOMP_ID__OFFSET 0x00000000u
#define CYFLD_LPCOMP_ID__SIZE 0x00000010u
#define CYFLD_LPCOMP_REVISION__OFFSET 0x00000010u
#define CYFLD_LPCOMP_REVISION__SIZE 0x00000010u
#define CYREG_LPCOMP_CONFIG 0x400a0004u
#define CYFLD_LPCOMP_MODE1__OFFSET 0x00000000u
#define CYFLD_LPCOMP_MODE1__SIZE 0x00000002u
#define CYVAL_LPCOMP_MODE1_SLOW 0x00000000u
#define CYVAL_LPCOMP_MODE1_FAST 0x00000001u
#define CYVAL_LPCOMP_MODE1_ULP 0x00000002u
#define CYFLD_LPCOMP_HYST1__OFFSET 0x00000002u
#define CYFLD_LPCOMP_HYST1__SIZE 0x00000001u
#define CYFLD_LPCOMP_FILTER1__OFFSET 0x00000003u
#define CYFLD_LPCOMP_FILTER1__SIZE 0x00000001u
#define CYFLD_LPCOMP_INTTYPE1__OFFSET 0x00000004u
#define CYFLD_LPCOMP_INTTYPE1__SIZE 0x00000002u
#define CYVAL_LPCOMP_INTTYPE1_DISABLE 0x00000000u
#define CYVAL_LPCOMP_INTTYPE1_RISING 0x00000001u
#define CYVAL_LPCOMP_INTTYPE1_FALLING 0x00000002u
#define CYVAL_LPCOMP_INTTYPE1_BOTH 0x00000003u
#define CYFLD_LPCOMP_OUT1__OFFSET 0x00000006u
#define CYFLD_LPCOMP_OUT1__SIZE 0x00000001u
#define CYFLD_LPCOMP_ENABLE1__OFFSET 0x00000007u
#define CYFLD_LPCOMP_ENABLE1__SIZE 0x00000001u
#define CYFLD_LPCOMP_MODE2__OFFSET 0x00000008u
#define CYFLD_LPCOMP_MODE2__SIZE 0x00000002u
#define CYVAL_LPCOMP_MODE2_SLOW 0x00000000u
#define CYVAL_LPCOMP_MODE2_FAST 0x00000001u
#define CYVAL_LPCOMP_MODE2_ULP 0x00000002u
#define CYFLD_LPCOMP_HYST2__OFFSET 0x0000000au
#define CYFLD_LPCOMP_HYST2__SIZE 0x00000001u
#define CYFLD_LPCOMP_FILTER2__OFFSET 0x0000000bu
#define CYFLD_LPCOMP_FILTER2__SIZE 0x00000001u
#define CYFLD_LPCOMP_INTTYPE2__OFFSET 0x0000000cu
#define CYFLD_LPCOMP_INTTYPE2__SIZE 0x00000002u
#define CYVAL_LPCOMP_INTTYPE2_DISABLE 0x00000000u
#define CYVAL_LPCOMP_INTTYPE2_RISING 0x00000001u
#define CYVAL_LPCOMP_INTTYPE2_FALLING 0x00000002u
#define CYVAL_LPCOMP_INTTYPE2_BOTH 0x00000003u
#define CYFLD_LPCOMP_OUT2__OFFSET 0x0000000eu
#define CYFLD_LPCOMP_OUT2__SIZE 0x00000001u
#define CYFLD_LPCOMP_ENABLE2__OFFSET 0x0000000fu
#define CYFLD_LPCOMP_ENABLE2__SIZE 0x00000001u
#define CYREG_LPCOMP_DFT 0x400a0008u
#define CYFLD_LPCOMP_CAL_EN__OFFSET 0x00000000u
#define CYFLD_LPCOMP_CAL_EN__SIZE 0x00000001u
#define CYFLD_LPCOMP_BYPASS__OFFSET 0x00000001u
#define CYFLD_LPCOMP_BYPASS__SIZE 0x00000001u
#define CYREG_LPCOMP_INTR 0x400a000cu
#define CYFLD_LPCOMP_COMP1__OFFSET 0x00000000u
#define CYFLD_LPCOMP_COMP1__SIZE 0x00000001u
#define CYFLD_LPCOMP_COMP2__OFFSET 0x00000001u
#define CYFLD_LPCOMP_COMP2__SIZE 0x00000001u
#define CYREG_LPCOMP_INTR_SET 0x400a0010u
#define CYREG_LPCOMP_TRIM1 0x400aff00u
#define CYFLD_LPCOMP_COMP1_TRIMA__OFFSET 0x00000000u
#define CYFLD_LPCOMP_COMP1_TRIMA__SIZE 0x00000005u
#define CYREG_LPCOMP_TRIM2 0x400aff04u
#define CYFLD_LPCOMP_COMP1_TRIMB__OFFSET 0x00000000u
#define CYFLD_LPCOMP_COMP1_TRIMB__SIZE 0x00000005u
#define CYREG_LPCOMP_TRIM3 0x400aff08u
#define CYFLD_LPCOMP_COMP2_TRIMA__OFFSET 0x00000000u
#define CYFLD_LPCOMP_COMP2_TRIMA__SIZE 0x00000005u
#define CYREG_LPCOMP_TRIM4 0x400aff0cu
#define CYFLD_LPCOMP_COMP2_TRIMB__OFFSET 0x00000000u
#define CYFLD_LPCOMP_COMP2_TRIMB__SIZE 0x00000005u
#define CYREG_PWR_CONTROL 0x400b0000u
#define CYFLD__POWER_MODE__OFFSET 0x00000000u
#define CYFLD__POWER_MODE__SIZE 0x00000004u
#define CYVAL__POWER_MODE_RESET 0x00000000u
#define CYVAL__POWER_MODE_ACTIVE 0x00000001u
#define CYVAL__POWER_MODE_SLEEP 0x00000002u
#define CYVAL__POWER_MODE_DEEP_SLEEP 0x00000003u
#define CYVAL__POWER_MODE_HIBERNATE 0x00000004u
#define CYFLD__DEBUG_SESSION__OFFSET 0x00000004u
#define CYFLD__DEBUG_SESSION__SIZE 0x00000001u
#define CYVAL__DEBUG_SESSION_NO_SESSION 0x00000000u
#define CYVAL__DEBUG_SESSION_SESSION_ACTIVE 0x00000001u
#define CYFLD__LPM_READY__OFFSET 0x00000005u
#define CYFLD__LPM_READY__SIZE 0x00000001u
#define CYFLD__EXT_VCCD__OFFSET 0x00000017u
#define CYFLD__EXT_VCCD__SIZE 0x00000001u
#define CYFLD__HVMON_ENABLE__OFFSET 0x00000018u
#define CYFLD__HVMON_ENABLE__SIZE 0x00000001u
#define CYFLD__HVMON_RELOAD__OFFSET 0x00000019u
#define CYFLD__HVMON_RELOAD__SIZE 0x00000001u
#define CYFLD__FIMO_DISABLE__OFFSET 0x0000001bu
#define CYFLD__FIMO_DISABLE__SIZE 0x00000001u
#define CYFLD__HIBERNATE_DISABLE__OFFSET 0x0000001cu
#define CYFLD__HIBERNATE_DISABLE__SIZE 0x00000001u
#define CYFLD__LFCLK_SHORT__OFFSET 0x0000001du
#define CYFLD__LFCLK_SHORT__SIZE 0x00000001u
#define CYFLD__HIBERNATE__OFFSET 0x0000001fu
#define CYFLD__HIBERNATE__SIZE 0x00000001u
#define CYVAL__HIBERNATE_DEEP_SLEEP 0x00000000u
#define CYVAL__HIBERNATE_HIBERNATE 0x00000001u
#define CYREG_PWR_INTR 0x400b0004u
#define CYFLD__LVD__OFFSET 0x00000001u
#define CYFLD__LVD__SIZE 0x00000001u
#define CYREG_PWR_INTR_MASK 0x400b0008u
#define CYREG_PWR_KEY_DELAY 0x400b000cu
#define CYFLD__WAKEUP_HOLDOFF__OFFSET 0x00000000u
#define CYFLD__WAKEUP_HOLDOFF__SIZE 0x0000000au
#define CYREG_PWR_PWRSYS_CONFIG 0x400b0010u
#define CYFLD__HIB_TEST_EN__OFFSET 0x00000008u
#define CYFLD__HIB_TEST_EN__SIZE 0x00000001u
#define CYFLD__HIB_TEST_REP__OFFSET 0x00000009u
#define CYFLD__HIB_TEST_REP__SIZE 0x00000001u
#define CYREG_PWR_BG_CONFIG 0x400b0014u
#define CYFLD__BG_DFT_EN__OFFSET 0x00000000u
#define CYFLD__BG_DFT_EN__SIZE 0x00000001u
#define CYFLD__BG_DFT_VREF_SEL__OFFSET 0x00000001u
#define CYFLD__BG_DFT_VREF_SEL__SIZE 0x00000004u
#define CYFLD__BG_DFT_CORE_SEL__OFFSET 0x00000005u
#define CYFLD__BG_DFT_CORE_SEL__SIZE 0x00000001u
#define CYFLD__BG_DFT_ICORE_SEL__OFFSET 0x00000006u
#define CYFLD__BG_DFT_ICORE_SEL__SIZE 0x00000002u
#define CYFLD__BG_DFT_VCORE_SEL__OFFSET 0x00000008u
#define CYFLD__BG_DFT_VCORE_SEL__SIZE 0x00000001u
#define CYFLD__VREF_EN__OFFSET 0x00000010u
#define CYFLD__VREF_EN__SIZE 0x00000003u
#define CYREG_PWR_VMON_CONFIG 0x400b0018u
#define CYFLD__LVD_EN__OFFSET 0x00000000u
#define CYFLD__LVD_EN__SIZE 0x00000001u
#define CYFLD__LVD_SEL__OFFSET 0x00000001u
#define CYFLD__LVD_SEL__SIZE 0x00000004u
#define CYFLD__VMON_DDFT_SEL__OFFSET 0x00000005u
#define CYFLD__VMON_DDFT_SEL__SIZE 0x00000003u
#define CYFLD__VMON_ADFT_SEL__OFFSET 0x00000008u
#define CYFLD__VMON_ADFT_SEL__SIZE 0x00000002u
#define CYREG_PWR_DFT_SELECT 0x400b001cu
#define CYFLD__TVMON1_SEL__OFFSET 0x00000000u
#define CYFLD__TVMON1_SEL__SIZE 0x00000003u
#define CYFLD__TVMON2_SEL__OFFSET 0x00000003u
#define CYFLD__TVMON2_SEL__SIZE 0x00000003u
#define CYFLD__BYPASS__OFFSET 0x00000006u
#define CYFLD__BYPASS__SIZE 0x00000001u
#define CYFLD__ACTIVE_EN__OFFSET 0x00000007u
#define CYFLD__ACTIVE_EN__SIZE 0x00000001u
#define CYFLD__ACTIVE_INRUSH_DIS__OFFSET 0x00000008u
#define CYFLD__ACTIVE_INRUSH_DIS__SIZE 0x00000001u
#define CYFLD__LPCOMP_DIS__OFFSET 0x00000009u
#define CYFLD__LPCOMP_DIS__SIZE 0x00000001u
#define CYFLD__BLEED_EN__OFFSET 0x0000000au
#define CYFLD__BLEED_EN__SIZE 0x00000001u
#define CYFLD__IPOR_EN__OFFSET 0x0000000bu
#define CYFLD__IPOR_EN__SIZE 0x00000001u
#define CYFLD__POWER_UP_RAW_BYP__OFFSET 0x0000000cu
#define CYFLD__POWER_UP_RAW_BYP__SIZE 0x00000001u
#define CYFLD__POWER_UP_RAW_CTL__OFFSET 0x0000000du
#define CYFLD__POWER_UP_RAW_CTL__SIZE 0x00000001u
#define CYFLD__DEEPSLEEP_EN__OFFSET 0x0000000eu
#define CYFLD__DEEPSLEEP_EN__SIZE 0x00000001u
#define CYFLD__RSVD_BYPASS__OFFSET 0x0000000fu
#define CYFLD__RSVD_BYPASS__SIZE 0x00000001u
#define CYFLD__NWELL_OPEN__OFFSET 0x00000010u
#define CYFLD__NWELL_OPEN__SIZE 0x00000001u
#define CYFLD__HIBERNATE_OPEN__OFFSET 0x00000011u
#define CYFLD__HIBERNATE_OPEN__SIZE 0x00000001u
#define CYFLD__DEEPSLEEP_OPEN__OFFSET 0x00000012u
#define CYFLD__DEEPSLEEP_OPEN__SIZE 0x00000001u
#define CYFLD__QUIET_OPEN__OFFSET 0x00000013u
#define CYFLD__QUIET_OPEN__SIZE 0x00000001u
#define CYFLD__LFCLK_OPEN__OFFSET 0x00000014u
#define CYFLD__LFCLK_OPEN__SIZE 0x00000001u
#define CYFLD__QUIET_EN__OFFSET 0x00000016u
#define CYFLD__QUIET_EN__SIZE 0x00000001u
#define CYFLD__BREF_EN__OFFSET 0x00000017u
#define CYFLD__BREF_EN__SIZE 0x00000001u
#define CYFLD__BREF_OUTEN__OFFSET 0x00000018u
#define CYFLD__BREF_OUTEN__SIZE 0x00000001u
#define CYFLD__BREF_REFSW__OFFSET 0x00000019u
#define CYFLD__BREF_REFSW__SIZE 0x00000001u
#define CYFLD__BREF_TESTMODE__OFFSET 0x0000001au
#define CYFLD__BREF_TESTMODE__SIZE 0x00000001u
#define CYFLD__NWELL_DIS__OFFSET 0x0000001bu
#define CYFLD__NWELL_DIS__SIZE 0x00000001u
#define CYFLD__HVMON_DFT_OVR__OFFSET 0x0000001cu
#define CYFLD__HVMON_DFT_OVR__SIZE 0x00000001u
#define CYFLD__IMO_REFGEN_DIS__OFFSET 0x0000001du
#define CYFLD__IMO_REFGEN_DIS__SIZE 0x00000001u
#define CYFLD__POWER_UP_ACTIVE__OFFSET 0x0000001eu
#define CYFLD__POWER_UP_ACTIVE__SIZE 0x00000001u
#define CYFLD__POWER_UP_HIBDPSLP__OFFSET 0x0000001fu
#define CYFLD__POWER_UP_HIBDPSLP__SIZE 0x00000001u
#define CYREG_PWR_DDFT_SELECT 0x400b0020u
#define CYFLD__DDFT1_SEL__OFFSET 0x00000000u
#define CYFLD__DDFT1_SEL__SIZE 0x00000004u
#define CYFLD__DDFT2_SEL__OFFSET 0x00000004u
#define CYFLD__DDFT2_SEL__SIZE 0x00000004u
#define CYREG_PWR_DFT_KEY 0x400b0024u
#define CYFLD__KEY16__OFFSET 0x00000000u
#define CYFLD__KEY16__SIZE 0x00000010u
#define CYFLD__HBOD_OFF_AWAKE__OFFSET 0x00000010u
#define CYFLD__HBOD_OFF_AWAKE__SIZE 0x00000001u
#define CYFLD__BODS_OFF__OFFSET 0x00000011u
#define CYFLD__BODS_OFF__SIZE 0x00000001u
#define CYFLD__DFT_MODE__OFFSET 0x00000012u
#define CYFLD__DFT_MODE__SIZE 0x00000001u
#define CYFLD__IO_DISABLE_BYPASS__OFFSET 0x00000013u
#define CYFLD__IO_DISABLE_BYPASS__SIZE 0x00000001u
#define CYFLD__VMON_PD__OFFSET 0x00000014u
#define CYFLD__VMON_PD__SIZE 0x00000001u
#define CYREG_PWR_BOD_KEY 0x400b0028u
#define CYREG_PWR_STOP 0x400b002cu
#define CYFLD__TOKEN__OFFSET 0x00000000u
#define CYFLD__TOKEN__SIZE 0x00000008u
#define CYFLD__UNLOCK__OFFSET 0x00000008u
#define CYFLD__UNLOCK__SIZE 0x00000008u
#define CYFLD__POLARITY__OFFSET 0x00000010u
#define CYFLD__POLARITY__SIZE 0x00000001u
#define CYFLD__FREEZE__OFFSET 0x00000011u
#define CYFLD__FREEZE__SIZE 0x00000001u
#define CYFLD__STOP__OFFSET 0x0000001fu
#define CYFLD__STOP__SIZE 0x00000001u
#define CYREG_CLK_SELECT 0x400b0100u
#define CYFLD__DIRECT_SEL__OFFSET 0x00000000u
#define CYFLD__DIRECT_SEL__SIZE 0x00000003u
#define CYVAL__DIRECT_SEL_IMO 0x00000000u
#define CYVAL__DIRECT_SEL_EXTCLK 0x00000001u
#define CYVAL__DIRECT_SEL_ECO 0x00000002u
#define CYVAL__DIRECT_SEL_DSI0 0x00000004u
#define CYVAL__DIRECT_SEL_DSI1 0x00000005u
#define CYVAL__DIRECT_SEL_DSI2 0x00000006u
#define CYVAL__DIRECT_SEL_DSI3 0x00000007u
#define CYFLD__DBL_SEL__OFFSET 0x00000003u
#define CYFLD__DBL_SEL__SIZE 0x00000003u
#define CYVAL__DBL_SEL_IMO 0x00000000u
#define CYVAL__DBL_SEL_EXTCLK 0x00000001u
#define CYVAL__DBL_SEL_ECO 0x00000002u
#define CYVAL__DBL_SEL_DSI0 0x00000004u
#define CYVAL__DBL_SEL_DSI1 0x00000005u
#define CYVAL__DBL_SEL_DSI2 0x00000006u
#define CYVAL__DBL_SEL_DSI3 0x00000007u
#define CYFLD__PLL_SEL__OFFSET 0x00000006u
#define CYFLD__PLL_SEL__SIZE 0x00000003u
#define CYVAL__PLL_SEL_IMO 0x00000000u
#define CYVAL__PLL_SEL_EXTCLK 0x00000001u
#define CYVAL__PLL_SEL_ECO 0x00000002u
#define CYVAL__PLL_SEL_DPLL 0x00000003u
#define CYVAL__PLL_SEL_DSI0 0x00000004u
#define CYVAL__PLL_SEL_DSI1 0x00000005u
#define CYVAL__PLL_SEL_DSI2 0x00000006u
#define CYVAL__PLL_SEL_DSI3 0x00000007u
#define CYFLD__DPLLIN_SEL__OFFSET 0x00000009u
#define CYFLD__DPLLIN_SEL__SIZE 0x00000003u
#define CYVAL__DPLLIN_SEL_IMO 0x00000000u
#define CYVAL__DPLLIN_SEL_EXTCLK 0x00000001u
#define CYVAL__DPLLIN_SEL_ECO 0x00000002u
#define CYVAL__DPLLIN_SEL_DSI0 0x00000004u
#define CYVAL__DPLLIN_SEL_DSI1 0x00000005u
#define CYVAL__DPLLIN_SEL_DSI2 0x00000006u
#define CYVAL__DPLLIN_SEL_DSI3 0x00000007u
#define CYFLD__DPLLREF_SEL__OFFSET 0x0000000cu
#define CYFLD__DPLLREF_SEL__SIZE 0x00000002u
#define CYVAL__DPLLREF_SEL_DSI0 0x00000000u
#define CYVAL__DPLLREF_SEL_DSI1 0x00000001u
#define CYVAL__DPLLREF_SEL_DSI2 0x00000002u
#define CYVAL__DPLLREF_SEL_DSI3 0x00000003u
#define CYFLD__WDT_LOCK__OFFSET 0x0000000eu
#define CYFLD__WDT_LOCK__SIZE 0x00000002u
#define CYVAL__WDT_LOCK_NO_CHG 0x00000000u
#define CYVAL__WDT_LOCK_CLR0 0x00000001u
#define CYVAL__WDT_LOCK_CLR1 0x00000002u
#define CYVAL__WDT_LOCK_SET01 0x00000003u
#define CYFLD__HFCLK_SEL__OFFSET 0x00000010u
#define CYFLD__HFCLK_SEL__SIZE 0x00000002u
#define CYVAL__HFCLK_SEL_DIRECT_SEL 0x00000000u
#define CYVAL__HFCLK_SEL_DBL 0x00000001u
#define CYVAL__HFCLK_SEL_PLL 0x00000002u
#define CYFLD__HALF_EN__OFFSET 0x00000012u
#define CYFLD__HALF_EN__SIZE 0x00000001u
#define CYFLD__SYSCLK_DIV__OFFSET 0x00000013u
#define CYFLD__SYSCLK_DIV__SIZE 0x00000003u
#define CYVAL__SYSCLK_DIV_NO_DIV 0x00000000u
#define CYVAL__SYSCLK_DIV_DIV_BY_2 0x00000001u
#define CYVAL__SYSCLK_DIV_DIV_BY_4 0x00000002u
#define CYVAL__SYSCLK_DIV_DIV_BY_8 0x00000003u
#define CYVAL__SYSCLK_DIV_DIV_BY_16 0x00000004u
#define CYVAL__SYSCLK_DIV_DIV_BY_32 0x00000005u
#define CYVAL__SYSCLK_DIV_DIV_BY_64 0x00000006u
#define CYVAL__SYSCLK_DIV_DIV_BY_128 0x00000007u
#define CYREG_CLK_ILO_CONFIG 0x400b0104u
#define CYFLD__PD_MODE__OFFSET 0x00000000u
#define CYFLD__PD_MODE__SIZE 0x00000001u
#define CYVAL__PD_MODE_SLEEP 0x00000000u
#define CYVAL__PD_MODE_COMA 0x00000001u
#define CYFLD__TURBO__OFFSET 0x00000001u
#define CYFLD__TURBO__SIZE 0x00000001u
#define CYFLD__SATBIAS__OFFSET 0x00000002u
#define CYFLD__SATBIAS__SIZE 0x00000001u
#define CYVAL__SATBIAS_SATURATED 0x00000000u
#define CYVAL__SATBIAS_SUBTHRESHOLD 0x00000001u
#define CYFLD__ENABLE__OFFSET 0x0000001fu
#define CYFLD__ENABLE__SIZE 0x00000001u
#define CYREG_CLK_IMO_CONFIG 0x400b0108u
#define CYFLD__FLASHPUMP_SEL__OFFSET 0x00000016u
#define CYFLD__FLASHPUMP_SEL__SIZE 0x00000001u
#define CYVAL__FLASHPUMP_SEL_GND 0x00000000u
#define CYVAL__FLASHPUMP_SEL_CLK36 0x00000001u
#define CYFLD__EN_FASTBIAS__OFFSET 0x00000017u
#define CYFLD__EN_FASTBIAS__SIZE 0x00000001u
#define CYFLD__TEST_FASTBIAS__OFFSET 0x00000018u
#define CYFLD__TEST_FASTBIAS__SIZE 0x00000001u
#define CYFLD__PUMP_SEL__OFFSET 0x00000019u
#define CYFLD__PUMP_SEL__SIZE 0x00000003u
#define CYVAL__PUMP_SEL_GND 0x00000000u
#define CYVAL__PUMP_SEL_IMO 0x00000001u
#define CYVAL__PUMP_SEL_DBL 0x00000002u
#define CYVAL__PUMP_SEL_CLK36 0x00000003u
#define CYVAL__PUMP_SEL_FF1 0x00000004u
#define CYFLD__TEST_USB_MODE__OFFSET 0x0000001cu
#define CYFLD__TEST_USB_MODE__SIZE 0x00000001u
#define CYFLD__EN_CLK36__OFFSET 0x0000001du
#define CYFLD__EN_CLK36__SIZE 0x00000001u
#define CYFLD__EN_CLK2X__OFFSET 0x0000001eu
#define CYFLD__EN_CLK2X__SIZE 0x00000001u
#define CYREG_CLK_IMO_SPREAD 0x400b010cu
#define CYFLD__SS_VALUE__OFFSET 0x00000000u
#define CYFLD__SS_VALUE__SIZE 0x00000005u
#define CYFLD__SS_MAX__OFFSET 0x00000008u
#define CYFLD__SS_MAX__SIZE 0x00000005u
#define CYFLD__SS_RANGE__OFFSET 0x0000001cu
#define CYFLD__SS_RANGE__SIZE 0x00000002u
#define CYVAL__SS_RANGE_M1 0x00000000u
#define CYVAL__SS_RANGE_M2 0x00000001u
#define CYVAL__SS_RANGE_M4 0x00000002u
#define CYFLD__SS_MODE__OFFSET 0x0000001eu
#define CYFLD__SS_MODE__SIZE 0x00000002u
#define CYVAL__SS_MODE_OFF 0x00000000u
#define CYVAL__SS_MODE_TRIANGLE 0x00000001u
#define CYVAL__SS_MODE_LFSR 0x00000002u
#define CYVAL__SS_MODE_DSI 0x00000003u
#define CYREG_CLK_DFT_SELECT 0x400b0110u
#define CYFLD__DFT_SEL1__OFFSET 0x00000000u
#define CYFLD__DFT_SEL1__SIZE 0x00000004u
#define CYVAL__DFT_SEL1_NC 0x00000000u
#define CYVAL__DFT_SEL1_ILO 0x00000001u
#define CYVAL__DFT_SEL1_WCO 0x00000002u
#define CYVAL__DFT_SEL1_IMO 0x00000003u
#define CYVAL__DFT_SEL1_ECO 0x00000004u
#define CYVAL__DFT_SEL1_PLL 0x00000005u
#define CYVAL__DFT_SEL1_DPLL_OUT 0x00000006u
#define CYVAL__DFT_SEL1_DPLL_REF 0x00000007u
#define CYVAL__DFT_SEL1_DBL 0x00000008u
#define CYVAL__DFT_SEL1_IMO2X 0x00000009u
#define CYVAL__DFT_SEL1_IMO36 0x0000000au
#define CYVAL__DFT_SEL1_HFCLK 0x0000000bu
#define CYVAL__DFT_SEL1_LFCLK 0x0000000cu
#define CYVAL__DFT_SEL1_SYSCLK 0x0000000du
#define CYVAL__DFT_SEL1_EXTCLK 0x0000000eu
#define CYVAL__DFT_SEL1_HALFSYSCLK 0x0000000fu
#define CYFLD__DFT_DIV1__OFFSET 0x00000004u
#define CYFLD__DFT_DIV1__SIZE 0x00000002u
#define CYVAL__DFT_DIV1_NO_DIV 0x00000000u
#define CYVAL__DFT_DIV1_DIV_BY_2 0x00000001u
#define CYVAL__DFT_DIV1_DIV_BY_4 0x00000002u
#define CYVAL__DFT_DIV1_DIV_BY_8 0x00000003u
#define CYFLD__DFT_SEL2__OFFSET 0x00000008u
#define CYFLD__DFT_SEL2__SIZE 0x00000004u
#define CYVAL__DFT_SEL2_NC 0x00000000u
#define CYVAL__DFT_SEL2_ILO 0x00000001u
#define CYVAL__DFT_SEL2_WCO 0x00000002u
#define CYVAL__DFT_SEL2_IMO 0x00000003u
#define CYVAL__DFT_SEL2_ECO 0x00000004u
#define CYVAL__DFT_SEL2_PLL 0x00000005u
#define CYVAL__DFT_SEL2_DPLL_OUT 0x00000006u
#define CYVAL__DFT_SEL2_DPLL_REF 0x00000007u
#define CYVAL__DFT_SEL2_DBL 0x00000008u
#define CYVAL__DFT_SEL2_IMO2X 0x00000009u
#define CYVAL__DFT_SEL2_IMO36 0x0000000au
#define CYVAL__DFT_SEL2_HFCLK 0x0000000bu
#define CYVAL__DFT_SEL2_LFCLK 0x0000000cu
#define CYVAL__DFT_SEL2_SYSCLK 0x0000000du
#define CYVAL__DFT_SEL2_EXTCLK 0x0000000eu
#define CYVAL__DFT_SEL2_HALFSYSCLK 0x0000000fu
#define CYFLD__DFT_DIV2__OFFSET 0x0000000cu
#define CYFLD__DFT_DIV2__SIZE 0x00000002u
#define CYVAL__DFT_DIV2_NO_DIV 0x00000000u
#define CYVAL__DFT_DIV2_DIV_BY_2 0x00000001u
#define CYVAL__DFT_DIV2_DIV_BY_4 0x00000002u
#define CYVAL__DFT_DIV2_DIV_BY_8 0x00000003u
#define CYREG_WDT_CTRLOW 0x400b0200u
#define CYFLD__WDT_CTR0__OFFSET 0x00000000u
#define CYFLD__WDT_CTR0__SIZE 0x00000010u
#define CYFLD__WDT_CTR1__OFFSET 0x00000010u
#define CYFLD__WDT_CTR1__SIZE 0x00000010u
#define CYREG_WDT_CTRHIGH 0x400b0204u
#define CYFLD__WDT_CTR2__OFFSET 0x00000000u
#define CYFLD__WDT_CTR2__SIZE 0x00000020u
#define CYREG_WDT_MATCH 0x400b0208u
#define CYFLD__WDT_MATCH0__OFFSET 0x00000000u
#define CYFLD__WDT_MATCH0__SIZE 0x00000010u
#define CYFLD__WDT_MATCH1__OFFSET 0x00000010u
#define CYFLD__WDT_MATCH1__SIZE 0x00000010u
#define CYREG_WDT_CONFIG 0x400b020cu
#define CYFLD__WDT_MODE0__OFFSET 0x00000000u
#define CYFLD__WDT_MODE0__SIZE 0x00000002u
#define CYVAL__WDT_MODE0_NOTHING 0x00000000u
#define CYVAL__WDT_MODE0_INT 0x00000001u
#define CYVAL__WDT_MODE0_RESET 0x00000002u
#define CYVAL__WDT_MODE0_INT_THEN_RESET 0x00000003u
#define CYFLD__WDT_CLEAR0__OFFSET 0x00000002u
#define CYFLD__WDT_CLEAR0__SIZE 0x00000001u
#define CYFLD__WDT_CASCADE0_1__OFFSET 0x00000003u
#define CYFLD__WDT_CASCADE0_1__SIZE 0x00000001u
#define CYFLD__WDT_MODE1__OFFSET 0x00000008u
#define CYFLD__WDT_MODE1__SIZE 0x00000002u
#define CYVAL__WDT_MODE1_NOTHING 0x00000000u
#define CYVAL__WDT_MODE1_INT 0x00000001u
#define CYVAL__WDT_MODE1_RESET 0x00000002u
#define CYVAL__WDT_MODE1_INT_THEN_RESET 0x00000003u
#define CYFLD__WDT_CLEAR1__OFFSET 0x0000000au
#define CYFLD__WDT_CLEAR1__SIZE 0x00000001u
#define CYFLD__WDT_CASCADE1_2__OFFSET 0x0000000bu
#define CYFLD__WDT_CASCADE1_2__SIZE 0x00000001u
#define CYFLD__WDT_MODE2__OFFSET 0x00000010u
#define CYFLD__WDT_MODE2__SIZE 0x00000001u
#define CYVAL__WDT_MODE2_NOTHING 0x00000000u
#define CYVAL__WDT_MODE2_INT 0x00000001u
#define CYFLD__WDT_BITS2__OFFSET 0x00000018u
#define CYFLD__WDT_BITS2__SIZE 0x00000005u
#define CYFLD__LFCLK_SEL__OFFSET 0x0000001eu
#define CYFLD__LFCLK_SEL__SIZE 0x00000002u
#define CYREG_WDT_CONTROL 0x400b0210u
#define CYFLD__WDT_ENABLE0__OFFSET 0x00000000u
#define CYFLD__WDT_ENABLE0__SIZE 0x00000001u
#define CYFLD__WDT_ENABLED0__OFFSET 0x00000001u
#define CYFLD__WDT_ENABLED0__SIZE 0x00000001u
#define CYFLD__WDT_INT0__OFFSET 0x00000002u
#define CYFLD__WDT_INT0__SIZE 0x00000001u
#define CYFLD__WDT_RESET0__OFFSET 0x00000003u
#define CYFLD__WDT_RESET0__SIZE 0x00000001u
#define CYFLD__WDT_ENABLE1__OFFSET 0x00000008u
#define CYFLD__WDT_ENABLE1__SIZE 0x00000001u
#define CYFLD__WDT_ENABLED1__OFFSET 0x00000009u
#define CYFLD__WDT_ENABLED1__SIZE 0x00000001u
#define CYFLD__WDT_INT1__OFFSET 0x0000000au
#define CYFLD__WDT_INT1__SIZE 0x00000001u
#define CYFLD__WDT_RESET1__OFFSET 0x0000000bu
#define CYFLD__WDT_RESET1__SIZE 0x00000001u
#define CYFLD__WDT_ENABLE2__OFFSET 0x00000010u
#define CYFLD__WDT_ENABLE2__SIZE 0x00000001u
#define CYFLD__WDT_ENABLED2__OFFSET 0x00000011u
#define CYFLD__WDT_ENABLED2__SIZE 0x00000001u
#define CYFLD__WDT_INT2__OFFSET 0x00000012u
#define CYFLD__WDT_INT2__SIZE 0x00000001u
#define CYFLD__WDT_RESET2__OFFSET 0x00000013u
#define CYFLD__WDT_RESET2__SIZE 0x00000001u
#define CYREG_RES_CAUSE 0x400b0300u
#define CYFLD__RESET_WDT__OFFSET 0x00000000u
#define CYFLD__RESET_WDT__SIZE 0x00000001u
#define CYFLD__RESET_DSBOD__OFFSET 0x00000001u
#define CYFLD__RESET_DSBOD__SIZE 0x00000001u
#define CYFLD__RESET_LOCKUP__OFFSET 0x00000002u
#define CYFLD__RESET_LOCKUP__SIZE 0x00000001u
#define CYFLD__RESET_PROT_FAULT__OFFSET 0x00000003u
#define CYFLD__RESET_PROT_FAULT__SIZE 0x00000001u
#define CYFLD__RESET_SOFT__OFFSET 0x00000004u
#define CYFLD__RESET_SOFT__SIZE 0x00000001u
#define CYFLD__RESET_HVBOD__OFFSET 0x00000005u
#define CYFLD__RESET_HVBOD__SIZE 0x00000001u
#define CYFLD__RESET_PBOD__OFFSET 0x00000006u
#define CYFLD__RESET_PBOD__SIZE 0x00000001u
#define CYFLD__RESET_XRES__OFFSET 0x00000007u
#define CYFLD__RESET_XRES__SIZE 0x00000001u
#define CYREG_PWR_PWRSYS_TRIM1 0x400bff00u
#define CYFLD__HIB_BIAS_TRIM__OFFSET 0x00000000u
#define CYFLD__HIB_BIAS_TRIM__SIZE 0x00000003u
#define CYFLD__BOD_TURBO_THRESH__OFFSET 0x00000003u
#define CYFLD__BOD_TURBO_THRESH__SIZE 0x00000001u
#define CYFLD__BOD_TRIM_TRIP__OFFSET 0x00000004u
#define CYFLD__BOD_TRIM_TRIP__SIZE 0x00000004u
#define CYREG_PWR_PWRSYS_TRIM2 0x400bff04u
#define CYFLD__LFCLK_TRIM_LOAD__OFFSET 0x00000000u
#define CYFLD__LFCLK_TRIM_LOAD__SIZE 0x00000002u
#define CYFLD__LFCLK_TRIM_VOLTAGE__OFFSET 0x00000002u
#define CYFLD__LFCLK_TRIM_VOLTAGE__SIZE 0x00000002u
#define CYFLD__DPSLP_TRIM_LOAD__OFFSET 0x00000004u
#define CYFLD__DPSLP_TRIM_LOAD__SIZE 0x00000002u
#define CYFLD__DPSLP_TRIM_LEAKAGE__OFFSET 0x00000006u
#define CYFLD__DPSLP_TRIM_LEAKAGE__SIZE 0x00000001u
#define CYFLD__DPSLP_TRIM_VOLTAGE__OFFSET 0x00000007u
#define CYFLD__DPSLP_TRIM_VOLTAGE__SIZE 0x00000001u
#define CYREG_PWR_PWRSYS_TRIM3 0x400bff08u
#define CYFLD__NWELL_TRIM__OFFSET 0x00000000u
#define CYFLD__NWELL_TRIM__SIZE 0x00000003u
#define CYFLD__QUIET_TRIM__OFFSET 0x00000003u
#define CYFLD__QUIET_TRIM__SIZE 0x00000005u
#define CYREG_PWR_PWRSYS_TRIM4 0x400bff0cu
#define CYFLD__HIB_TRIM_NWELL__OFFSET 0x00000000u
#define CYFLD__HIB_TRIM_NWELL__SIZE 0x00000002u
#define CYFLD__HIB_TRIM_LEAKAGE__OFFSET 0x00000002u
#define CYFLD__HIB_TRIM_LEAKAGE__SIZE 0x00000001u
#define CYFLD__HIB_TRIM_VOLTAGE__OFFSET 0x00000003u
#define CYFLD__HIB_TRIM_VOLTAGE__SIZE 0x00000001u
#define CYFLD__HIB_TRIM_REFERENCE__OFFSET 0x00000004u
#define CYFLD__HIB_TRIM_REFERENCE__SIZE 0x00000002u
#define CYREG_PWR_BG_TRIM1 0x400bff10u
#define CYFLD__INL_TRIM_MAIN__OFFSET 0x00000000u
#define CYFLD__INL_TRIM_MAIN__SIZE 0x00000003u
#define CYFLD__INL_CROSS_MAIN__OFFSET 0x00000003u
#define CYFLD__INL_CROSS_MAIN__SIZE 0x00000004u
#define CYREG_PWR_BG_TRIM2 0x400bff14u
#define CYFLD__VCTAT_SLOPE__OFFSET 0x00000000u
#define CYFLD__VCTAT_SLOPE__SIZE 0x00000004u
#define CYFLD__VCTAT_VOLTAGE__OFFSET 0x00000004u
#define CYFLD__VCTAT_VOLTAGE__SIZE 0x00000002u
#define CYFLD__VCTAT_ENABLE__OFFSET 0x00000006u
#define CYFLD__VCTAT_ENABLE__SIZE 0x00000001u
#define CYFLD__VCTAT_VOLTAGE_MSB__OFFSET 0x00000007u
#define CYFLD__VCTAT_VOLTAGE_MSB__SIZE 0x00000001u
#define CYREG_PWR_BG_TRIM3 0x400bff18u
#define CYFLD__INL_TRIM_IMO__OFFSET 0x00000000u
#define CYFLD__INL_TRIM_IMO__SIZE 0x00000003u
#define CYFLD__INL_CROSS_IMO__OFFSET 0x00000003u
#define CYFLD__INL_CROSS_IMO__SIZE 0x00000004u
#define CYREG_PWR_BG_TRIM4 0x400bff1cu
#define CYFLD__ABS_TRIM_IMO__OFFSET 0x00000000u
#define CYFLD__ABS_TRIM_IMO__SIZE 0x00000006u
#define CYREG_PWR_BG_TRIM5 0x400bff20u
#define CYFLD__TMPCO_TRIM_IMO__OFFSET 0x00000000u
#define CYFLD__TMPCO_TRIM_IMO__SIZE 0x00000006u
#define CYREG_CLK_ILO_TRIM 0x400bff24u
#define CYFLD__TRIM__OFFSET 0x00000000u
#define CYFLD__TRIM__SIZE 0x00000004u
#define CYFLD__COARSE_TRIM__OFFSET 0x00000004u
#define CYFLD__COARSE_TRIM__SIZE 0x00000004u
#define CYREG_CLK_IMO_TRIM1 0x400bff28u
#define CYFLD__OFFSET__OFFSET 0x00000000u
#define CYFLD__OFFSET__SIZE 0x00000008u
#define CYREG_CLK_IMO_TRIM2 0x400bff2cu
#define CYFLD__FREQ__OFFSET 0x00000000u
#define CYFLD__FREQ__SIZE 0x00000006u
#define CYREG_CLK_IMO_TRIM3 0x400bff30u
#define CYFLD__TRIM_CLK36__OFFSET 0x00000000u
#define CYFLD__TRIM_CLK36__SIZE 0x00000004u
#define CYREG_CLK_IMO_TRIM4 0x400bff34u
#define CYFLD__GAIN__OFFSET 0x00000000u
#define CYFLD__GAIN__SIZE 0x00000005u
#define CYFLD__FSOFFSET__OFFSET 0x00000005u
#define CYFLD__FSOFFSET__SIZE 0x00000003u
#define CYREG_PWR_RSVD_TRIM 0x400bff38u
#define CYFLD__RSVD_TRIM__OFFSET 0x00000000u
#define CYFLD__RSVD_TRIM__SIZE 0x00000004u
#define CYDEV_SPCIF_BASE 0x400e0000u
#define CYDEV_SPCIF_SIZE 0x00010000u
#define CYREG_SPCIF_GEOMETRY 0x400e0000u
#define CYFLD_SPCIF_FLASH__OFFSET 0x00000000u
#define CYFLD_SPCIF_FLASH__SIZE 0x00000010u
#define CYFLD_SPCIF_SFLASH__OFFSET 0x00000010u
#define CYFLD_SPCIF_SFLASH__SIZE 0x00000004u
#define CYFLD_SPCIF_NUM_FLASH__OFFSET 0x00000014u
#define CYFLD_SPCIF_NUM_FLASH__SIZE 0x00000002u
#define CYFLD_SPCIF_FLASH_ROW__OFFSET 0x00000016u
#define CYFLD_SPCIF_FLASH_ROW__SIZE 0x00000002u
#define CYFLD_SPCIF_NVL__OFFSET 0x00000018u
#define CYFLD_SPCIF_NVL__SIZE 0x00000007u
#define CYFLD_SPCIF_DE_CPD_LP__OFFSET 0x0000001fu
#define CYFLD_SPCIF_DE_CPD_LP__SIZE 0x00000001u
#define CYREG_SPCIF_NVL_WR_DATA 0x400e001cu
#define CYFLD_SPCIF_DATA__OFFSET 0x00000000u
#define CYFLD_SPCIF_DATA__SIZE 0x00000008u
#define CYDEV_UDB_BASE 0x400f0000u
#define CYDEV_UDB_SIZE 0x00010000u
#define CYDEV_UDB_W8_BASE 0x400f0000u
#define CYDEV_UDB_W8_SIZE 0x00001000u
#define CYREG_UDB_W8_A0_00 0x400f0000u
#define CYFLD_UDB_W8_A0__OFFSET 0x00000000u
#define CYFLD_UDB_W8_A0__SIZE 0x00000008u
#define CYREG_UDB_W8_A0_01 0x400f0001u
#define CYREG_UDB_W8_A0_02 0x400f0002u
#define CYREG_UDB_W8_A0_03 0x400f0003u
#define CYREG_UDB_W8_A1_00 0x400f0010u
#define CYFLD_UDB_W8_A1__OFFSET 0x00000000u
#define CYFLD_UDB_W8_A1__SIZE 0x00000008u
#define CYREG_UDB_W8_A1_01 0x400f0011u
#define CYREG_UDB_W8_A1_02 0x400f0012u
#define CYREG_UDB_W8_A1_03 0x400f0013u
#define CYREG_UDB_W8_D0_00 0x400f0020u
#define CYFLD_UDB_W8_D0__OFFSET 0x00000000u
#define CYFLD_UDB_W8_D0__SIZE 0x00000008u
#define CYREG_UDB_W8_D0_01 0x400f0021u
#define CYREG_UDB_W8_D0_02 0x400f0022u
#define CYREG_UDB_W8_D0_03 0x400f0023u
#define CYREG_UDB_W8_D1_00 0x400f0030u
#define CYFLD_UDB_W8_D1__OFFSET 0x00000000u
#define CYFLD_UDB_W8_D1__SIZE 0x00000008u
#define CYREG_UDB_W8_D1_01 0x400f0031u
#define CYREG_UDB_W8_D1_02 0x400f0032u
#define CYREG_UDB_W8_D1_03 0x400f0033u
#define CYREG_UDB_W8_F0_00 0x400f0040u
#define CYFLD_UDB_W8_F0__OFFSET 0x00000000u
#define CYFLD_UDB_W8_F0__SIZE 0x00000008u
#define CYREG_UDB_W8_F0_01 0x400f0041u
#define CYREG_UDB_W8_F0_02 0x400f0042u
#define CYREG_UDB_W8_F0_03 0x400f0043u
#define CYREG_UDB_W8_F1_00 0x400f0050u
#define CYFLD_UDB_W8_F1__OFFSET 0x00000000u
#define CYFLD_UDB_W8_F1__SIZE 0x00000008u
#define CYREG_UDB_W8_F1_01 0x400f0051u
#define CYREG_UDB_W8_F1_02 0x400f0052u
#define CYREG_UDB_W8_F1_03 0x400f0053u
#define CYREG_UDB_W8_ST_00 0x400f0060u
#define CYFLD_UDB_W8_ST__OFFSET 0x00000000u
#define CYFLD_UDB_W8_ST__SIZE 0x00000008u
#define CYREG_UDB_W8_ST_01 0x400f0061u
#define CYREG_UDB_W8_ST_02 0x400f0062u
#define CYREG_UDB_W8_ST_03 0x400f0063u
#define CYREG_UDB_W8_CTL_00 0x400f0070u
#define CYFLD_UDB_W8_CTL__OFFSET 0x00000000u
#define CYFLD_UDB_W8_CTL__SIZE 0x00000008u
#define CYREG_UDB_W8_CTL_01 0x400f0071u
#define CYREG_UDB_W8_CTL_02 0x400f0072u
#define CYREG_UDB_W8_CTL_03 0x400f0073u
#define CYREG_UDB_W8_MSK_00 0x400f0080u
#define CYFLD_UDB_W8_MSK__OFFSET 0x00000000u
#define CYFLD_UDB_W8_MSK__SIZE 0x00000007u
#define CYREG_UDB_W8_MSK_01 0x400f0081u
#define CYREG_UDB_W8_MSK_02 0x400f0082u
#define CYREG_UDB_W8_MSK_03 0x400f0083u
#define CYREG_UDB_W8_ACTL_00 0x400f0090u
#define CYFLD_UDB_W8_FIFO0_CLR__OFFSET 0x00000000u
#define CYFLD_UDB_W8_FIFO0_CLR__SIZE 0x00000001u
#define CYVAL_UDB_W8_FIFO0_CLR_NORMAL 0x00000000u
#define CYVAL_UDB_W8_FIFO0_CLR_CLEAR 0x00000001u
#define CYFLD_UDB_W8_FIFO1_CLR__OFFSET 0x00000001u
#define CYFLD_UDB_W8_FIFO1_CLR__SIZE 0x00000001u
#define CYVAL_UDB_W8_FIFO1_CLR_NORMAL 0x00000000u
#define CYVAL_UDB_W8_FIFO1_CLR_CLEAR 0x00000001u
#define CYFLD_UDB_W8_FIFO0_LVL__OFFSET 0x00000002u
#define CYFLD_UDB_W8_FIFO0_LVL__SIZE 0x00000001u
#define CYVAL_UDB_W8_FIFO0_LVL_NORMAL 0x00000000u
#define CYVAL_UDB_W8_FIFO0_LVL_MID 0x00000001u
#define CYFLD_UDB_W8_FIFO1_LVL__OFFSET 0x00000003u
#define CYFLD_UDB_W8_FIFO1_LVL__SIZE 0x00000001u
#define CYVAL_UDB_W8_FIFO1_LVL_NORMAL 0x00000000u
#define CYVAL_UDB_W8_FIFO1_LVL_MID 0x00000001u
#define CYFLD_UDB_W8_INT_EN__OFFSET 0x00000004u
#define CYFLD_UDB_W8_INT_EN__SIZE 0x00000001u
#define CYVAL_UDB_W8_INT_EN_DISABLE 0x00000000u
#define CYVAL_UDB_W8_INT_EN_ENABLE 0x00000001u
#define CYFLD_UDB_W8_CNT_START__OFFSET 0x00000005u
#define CYFLD_UDB_W8_CNT_START__SIZE 0x00000001u
#define CYVAL_UDB_W8_CNT_START_DISABLE 0x00000000u
#define CYVAL_UDB_W8_CNT_START_ENABLE 0x00000001u
#define CYREG_UDB_W8_ACTL_01 0x400f0091u
#define CYREG_UDB_W8_ACTL_02 0x400f0092u
#define CYREG_UDB_W8_ACTL_03 0x400f0093u
#define CYREG_UDB_W8_MC_00 0x400f00a0u
#define CYFLD_UDB_W8_PLD0_MC__OFFSET 0x00000000u
#define CYFLD_UDB_W8_PLD0_MC__SIZE 0x00000004u
#define CYFLD_UDB_W8_PLD1_MC__OFFSET 0x00000004u
#define CYFLD_UDB_W8_PLD1_MC__SIZE 0x00000004u
#define CYREG_UDB_W8_MC_01 0x400f00a1u
#define CYREG_UDB_W8_MC_02 0x400f00a2u
#define CYREG_UDB_W8_MC_03 0x400f00a3u
#define CYDEV_UDB_CAT16_BASE 0x400f1000u
#define CYDEV_UDB_CAT16_SIZE 0x00001000u
#define CYREG_UDB_CAT16_A_00 0x400f1000u
#define CYFLD_UDB_CAT16_A0__OFFSET 0x00000000u
#define CYFLD_UDB_CAT16_A0__SIZE 0x00000008u
#define CYFLD_UDB_CAT16_A1__OFFSET 0x00000008u
#define CYFLD_UDB_CAT16_A1__SIZE 0x00000008u
#define CYREG_UDB_CAT16_A_01 0x400f1002u
#define CYREG_UDB_CAT16_A_02 0x400f1004u
#define CYREG_UDB_CAT16_A_03 0x400f1006u
#define CYREG_UDB_CAT16_D_00 0x400f1040u
#define CYFLD_UDB_CAT16_D0__OFFSET 0x00000000u
#define CYFLD_UDB_CAT16_D0__SIZE 0x00000008u
#define CYFLD_UDB_CAT16_D1__OFFSET 0x00000008u
#define CYFLD_UDB_CAT16_D1__SIZE 0x00000008u
#define CYREG_UDB_CAT16_D_01 0x400f1042u
#define CYREG_UDB_CAT16_D_02 0x400f1044u
#define CYREG_UDB_CAT16_D_03 0x400f1046u
#define CYREG_UDB_CAT16_F_00 0x400f1080u
#define CYFLD_UDB_CAT16_F0__OFFSET 0x00000000u
#define CYFLD_UDB_CAT16_F0__SIZE 0x00000008u
#define CYFLD_UDB_CAT16_F1__OFFSET 0x00000008u
#define CYFLD_UDB_CAT16_F1__SIZE 0x00000008u
#define CYREG_UDB_CAT16_F_01 0x400f1082u
#define CYREG_UDB_CAT16_F_02 0x400f1084u
#define CYREG_UDB_CAT16_F_03 0x400f1086u
#define CYREG_UDB_CAT16_CTL_ST_00 0x400f10c0u
#define CYFLD_UDB_CAT16_ST__OFFSET 0x00000000u
#define CYFLD_UDB_CAT16_ST__SIZE 0x00000008u
#define CYFLD_UDB_CAT16_CTL__OFFSET 0x00000008u
#define CYFLD_UDB_CAT16_CTL__SIZE 0x00000008u
#define CYREG_UDB_CAT16_CTL_ST_01 0x400f10c2u
#define CYREG_UDB_CAT16_CTL_ST_02 0x400f10c4u
#define CYREG_UDB_CAT16_CTL_ST_03 0x400f10c6u
#define CYREG_UDB_CAT16_ACTL_MSK_00 0x400f1100u
#define CYFLD_UDB_CAT16_MSK__OFFSET 0x00000000u
#define CYFLD_UDB_CAT16_MSK__SIZE 0x00000008u
#define CYFLD_UDB_CAT16_FIFO0_CLR__OFFSET 0x00000008u
#define CYFLD_UDB_CAT16_FIFO0_CLR__SIZE 0x00000001u
#define CYVAL_UDB_CAT16_FIFO0_CLR_NORMAL 0x00000000u
#define CYVAL_UDB_CAT16_FIFO0_CLR_CLEAR 0x00000001u
#define CYFLD_UDB_CAT16_FIFO1_CLR__OFFSET 0x00000009u
#define CYFLD_UDB_CAT16_FIFO1_CLR__SIZE 0x00000001u
#define CYVAL_UDB_CAT16_FIFO1_CLR_NORMAL 0x00000000u
#define CYVAL_UDB_CAT16_FIFO1_CLR_CLEAR 0x00000001u
#define CYFLD_UDB_CAT16_FIFO0_LVL__OFFSET 0x0000000au
#define CYFLD_UDB_CAT16_FIFO0_LVL__SIZE 0x00000001u
#define CYVAL_UDB_CAT16_FIFO0_LVL_NORMAL 0x00000000u
#define CYVAL_UDB_CAT16_FIFO0_LVL_MID 0x00000001u
#define CYFLD_UDB_CAT16_FIFO1_LVL__OFFSET 0x0000000bu
#define CYFLD_UDB_CAT16_FIFO1_LVL__SIZE 0x00000001u
#define CYVAL_UDB_CAT16_FIFO1_LVL_NORMAL 0x00000000u
#define CYVAL_UDB_CAT16_FIFO1_LVL_MID 0x00000001u
#define CYFLD_UDB_CAT16_INT_EN__OFFSET 0x0000000cu
#define CYFLD_UDB_CAT16_INT_EN__SIZE 0x00000001u
#define CYVAL_UDB_CAT16_INT_EN_DISABLE 0x00000000u
#define CYVAL_UDB_CAT16_INT_EN_ENABLE 0x00000001u
#define CYFLD_UDB_CAT16_CNT_START__OFFSET 0x0000000du
#define CYFLD_UDB_CAT16_CNT_START__SIZE 0x00000001u
#define CYVAL_UDB_CAT16_CNT_START_DISABLE 0x00000000u
#define CYVAL_UDB_CAT16_CNT_START_ENABLE 0x00000001u
#define CYREG_UDB_CAT16_ACTL_MSK_01 0x400f1102u
#define CYREG_UDB_CAT16_ACTL_MSK_02 0x400f1104u
#define CYREG_UDB_CAT16_ACTL_MSK_03 0x400f1106u
#define CYREG_UDB_CAT16_MC_00 0x400f1140u
#define CYFLD_UDB_CAT16_PLD0_MC__OFFSET 0x00000000u
#define CYFLD_UDB_CAT16_PLD0_MC__SIZE 0x00000004u
#define CYFLD_UDB_CAT16_PLD1_MC__OFFSET 0x00000004u
#define CYFLD_UDB_CAT16_PLD1_MC__SIZE 0x00000004u
#define CYREG_UDB_CAT16_MC_01 0x400f1142u
#define CYREG_UDB_CAT16_MC_02 0x400f1144u
#define CYREG_UDB_CAT16_MC_03 0x400f1146u
#define CYDEV_UDB_W16_BASE 0x400f1000u
#define CYDEV_UDB_W16_SIZE 0x00001000u
#define CYREG_UDB_W16_A0_00 0x400f1000u
#define CYFLD_UDB_W16_A0_LS__OFFSET 0x00000000u
#define CYFLD_UDB_W16_A0_LS__SIZE 0x00000008u
#define CYFLD_UDB_W16_A0_MS__OFFSET 0x00000008u
#define CYFLD_UDB_W16_A0_MS__SIZE 0x00000008u
#define CYREG_UDB_W16_A0_01 0x400f1002u
#define CYREG_UDB_W16_A0_02 0x400f1004u
#define CYREG_UDB_W16_A1_00 0x400f1020u
#define CYFLD_UDB_W16_A1_LS__OFFSET 0x00000000u
#define CYFLD_UDB_W16_A1_LS__SIZE 0x00000008u
#define CYFLD_UDB_W16_A1_MS__OFFSET 0x00000008u
#define CYFLD_UDB_W16_A1_MS__SIZE 0x00000008u
#define CYREG_UDB_W16_A1_01 0x400f1022u
#define CYREG_UDB_W16_A1_02 0x400f1024u
#define CYREG_UDB_W16_D0_00 0x400f1040u
#define CYFLD_UDB_W16_D0_LS__OFFSET 0x00000000u
#define CYFLD_UDB_W16_D0_LS__SIZE 0x00000008u
#define CYFLD_UDB_W16_D0_MS__OFFSET 0x00000008u
#define CYFLD_UDB_W16_D0_MS__SIZE 0x00000008u
#define CYREG_UDB_W16_D0_01 0x400f1042u
#define CYREG_UDB_W16_D0_02 0x400f1044u
#define CYREG_UDB_W16_D1_00 0x400f1060u
#define CYFLD_UDB_W16_D1_LS__OFFSET 0x00000000u
#define CYFLD_UDB_W16_D1_LS__SIZE 0x00000008u
#define CYFLD_UDB_W16_D1_MS__OFFSET 0x00000008u
#define CYFLD_UDB_W16_D1_MS__SIZE 0x00000008u
#define CYREG_UDB_W16_D1_01 0x400f1062u
#define CYREG_UDB_W16_D1_02 0x400f1064u
#define CYREG_UDB_W16_F0_00 0x400f1080u
#define CYFLD_UDB_W16_F0_LS__OFFSET 0x00000000u
#define CYFLD_UDB_W16_F0_LS__SIZE 0x00000008u
#define CYFLD_UDB_W16_F0_MS__OFFSET 0x00000008u
#define CYFLD_UDB_W16_F0_MS__SIZE 0x00000008u
#define CYREG_UDB_W16_F0_01 0x400f1082u
#define CYREG_UDB_W16_F0_02 0x400f1084u
#define CYREG_UDB_W16_F1_00 0x400f10a0u
#define CYFLD_UDB_W16_F1_LS__OFFSET 0x00000000u
#define CYFLD_UDB_W16_F1_LS__SIZE 0x00000008u
#define CYFLD_UDB_W16_F1_MS__OFFSET 0x00000008u
#define CYFLD_UDB_W16_F1_MS__SIZE 0x00000008u
#define CYREG_UDB_W16_F1_01 0x400f10a2u
#define CYREG_UDB_W16_F1_02 0x400f10a4u
#define CYREG_UDB_W16_ST_00 0x400f10c0u
#define CYFLD_UDB_W16_ST_LS__OFFSET 0x00000000u
#define CYFLD_UDB_W16_ST_LS__SIZE 0x00000008u
#define CYFLD_UDB_W16_ST_MS__OFFSET 0x00000008u
#define CYFLD_UDB_W16_ST_MS__SIZE 0x00000008u
#define CYREG_UDB_W16_ST_01 0x400f10c2u
#define CYREG_UDB_W16_ST_02 0x400f10c4u
#define CYREG_UDB_W16_CTL_00 0x400f10e0u
#define CYFLD_UDB_W16_CTL_LS__OFFSET 0x00000000u
#define CYFLD_UDB_W16_CTL_LS__SIZE 0x00000008u
#define CYFLD_UDB_W16_CTL_MS__OFFSET 0x00000008u
#define CYFLD_UDB_W16_CTL_MS__SIZE 0x00000008u
#define CYREG_UDB_W16_CTL_01 0x400f10e2u
#define CYREG_UDB_W16_CTL_02 0x400f10e4u
#define CYREG_UDB_W16_MSK_00 0x400f1100u
#define CYFLD_UDB_W16_MSK_LS__OFFSET 0x00000000u
#define CYFLD_UDB_W16_MSK_LS__SIZE 0x00000007u
#define CYFLD_UDB_W16_MSK_MS__OFFSET 0x00000008u
#define CYFLD_UDB_W16_MSK_MS__SIZE 0x00000007u
#define CYREG_UDB_W16_MSK_01 0x400f1102u
#define CYREG_UDB_W16_MSK_02 0x400f1104u
#define CYREG_UDB_W16_ACTL_00 0x400f1120u
#define CYFLD_UDB_W16_FIFO0_CLR_LS__OFFSET 0x00000000u
#define CYFLD_UDB_W16_FIFO0_CLR_LS__SIZE 0x00000001u
#define CYVAL_UDB_W16_FIFO0_CLR_LS_NORMAL 0x00000000u
#define CYVAL_UDB_W16_FIFO0_CLR_LS_CLEAR 0x00000001u
#define CYFLD_UDB_W16_FIFO1_CLR_LS__OFFSET 0x00000001u
#define CYFLD_UDB_W16_FIFO1_CLR_LS__SIZE 0x00000001u
#define CYVAL_UDB_W16_FIFO1_CLR_LS_NORMAL 0x00000000u
#define CYVAL_UDB_W16_FIFO1_CLR_LS_CLEAR 0x00000001u
#define CYFLD_UDB_W16_FIFO0_LVL_LS__OFFSET 0x00000002u
#define CYFLD_UDB_W16_FIFO0_LVL_LS__SIZE 0x00000001u
#define CYVAL_UDB_W16_FIFO0_LVL_LS_NORMAL 0x00000000u
#define CYVAL_UDB_W16_FIFO0_LVL_LS_MID 0x00000001u
#define CYFLD_UDB_W16_FIFO1_LVL_LS__OFFSET 0x00000003u
#define CYFLD_UDB_W16_FIFO1_LVL_LS__SIZE 0x00000001u
#define CYVAL_UDB_W16_FIFO1_LVL_LS_NORMAL 0x00000000u
#define CYVAL_UDB_W16_FIFO1_LVL_LS_MID 0x00000001u
#define CYFLD_UDB_W16_INT_EN_LS__OFFSET 0x00000004u
#define CYFLD_UDB_W16_INT_EN_LS__SIZE 0x00000001u
#define CYVAL_UDB_W16_INT_EN_LS_DISABLE 0x00000000u
#define CYVAL_UDB_W16_INT_EN_LS_ENABLE 0x00000001u
#define CYFLD_UDB_W16_CNT_START_LS__OFFSET 0x00000005u
#define CYFLD_UDB_W16_CNT_START_LS__SIZE 0x00000001u
#define CYVAL_UDB_W16_CNT_START_LS_DISABLE 0x00000000u
#define CYVAL_UDB_W16_CNT_START_LS_ENABLE 0x00000001u
#define CYFLD_UDB_W16_FIFO0_CLR_MS__OFFSET 0x00000008u
#define CYFLD_UDB_W16_FIFO0_CLR_MS__SIZE 0x00000001u
#define CYVAL_UDB_W16_FIFO0_CLR_MS_NORMAL 0x00000000u
#define CYVAL_UDB_W16_FIFO0_CLR_MS_CLEAR 0x00000001u
#define CYFLD_UDB_W16_FIFO1_CLR_MS__OFFSET 0x00000009u
#define CYFLD_UDB_W16_FIFO1_CLR_MS__SIZE 0x00000001u
#define CYVAL_UDB_W16_FIFO1_CLR_MS_NORMAL 0x00000000u
#define CYVAL_UDB_W16_FIFO1_CLR_MS_CLEAR 0x00000001u
#define CYFLD_UDB_W16_FIFO0_LVL_MS__OFFSET 0x0000000au
#define CYFLD_UDB_W16_FIFO0_LVL_MS__SIZE 0x00000001u
#define CYVAL_UDB_W16_FIFO0_LVL_MS_NORMAL 0x00000000u
#define CYVAL_UDB_W16_FIFO0_LVL_MS_MID 0x00000001u
#define CYFLD_UDB_W16_FIFO1_LVL_MS__OFFSET 0x0000000bu
#define CYFLD_UDB_W16_FIFO1_LVL_MS__SIZE 0x00000001u
#define CYVAL_UDB_W16_FIFO1_LVL_MS_NORMAL 0x00000000u
#define CYVAL_UDB_W16_FIFO1_LVL_MS_MID 0x00000001u
#define CYFLD_UDB_W16_INT_EN_MS__OFFSET 0x0000000cu
#define CYFLD_UDB_W16_INT_EN_MS__SIZE 0x00000001u
#define CYVAL_UDB_W16_INT_EN_MS_DISABLE 0x00000000u
#define CYVAL_UDB_W16_INT_EN_MS_ENABLE 0x00000001u
#define CYFLD_UDB_W16_CNT_START_MS__OFFSET 0x0000000du
#define CYFLD_UDB_W16_CNT_START_MS__SIZE 0x00000001u
#define CYVAL_UDB_W16_CNT_START_MS_DISABLE 0x00000000u
#define CYVAL_UDB_W16_CNT_START_MS_ENABLE 0x00000001u
#define CYREG_UDB_W16_ACTL_01 0x400f1122u
#define CYREG_UDB_W16_ACTL_02 0x400f1124u
#define CYREG_UDB_W16_MC_00 0x400f1140u
#define CYFLD_UDB_W16_PLD0_MC_LS__OFFSET 0x00000000u
#define CYFLD_UDB_W16_PLD0_MC_LS__SIZE 0x00000004u
#define CYFLD_UDB_W16_PLD1_MC_LS__OFFSET 0x00000004u
#define CYFLD_UDB_W16_PLD1_MC_LS__SIZE 0x00000004u
#define CYFLD_UDB_W16_PLD0_MC_MS__OFFSET 0x00000008u
#define CYFLD_UDB_W16_PLD0_MC_MS__SIZE 0x00000004u
#define CYFLD_UDB_W16_PLD1_MC_MS__OFFSET 0x0000000cu
#define CYFLD_UDB_W16_PLD1_MC_MS__SIZE 0x00000004u
#define CYREG_UDB_W16_MC_01 0x400f1142u
#define CYREG_UDB_W16_MC_02 0x400f1144u
#define CYDEV_UDB_W32_BASE 0x400f2000u
#define CYDEV_UDB_W32_SIZE 0x00001000u
#define CYREG_UDB_W32_A0_00 0x400f2000u
#define CYFLD_UDB_W32_A0_0__OFFSET 0x00000000u
#define CYFLD_UDB_W32_A0_0__SIZE 0x00000008u
#define CYFLD_UDB_W32_A0_1__OFFSET 0x00000008u
#define CYFLD_UDB_W32_A0_1__SIZE 0x00000008u
#define CYFLD_UDB_W32_A0_2__OFFSET 0x00000010u
#define CYFLD_UDB_W32_A0_2__SIZE 0x00000008u
#define CYFLD_UDB_W32_A0_3__OFFSET 0x00000018u
#define CYFLD_UDB_W32_A0_3__SIZE 0x00000008u
#define CYREG_UDB_W32_A1_00 0x400f2040u
#define CYFLD_UDB_W32_A1_0__OFFSET 0x00000000u
#define CYFLD_UDB_W32_A1_0__SIZE 0x00000008u
#define CYFLD_UDB_W32_A1_1__OFFSET 0x00000008u
#define CYFLD_UDB_W32_A1_1__SIZE 0x00000008u
#define CYFLD_UDB_W32_A1_2__OFFSET 0x00000010u
#define CYFLD_UDB_W32_A1_2__SIZE 0x00000008u
#define CYFLD_UDB_W32_A1_3__OFFSET 0x00000018u
#define CYFLD_UDB_W32_A1_3__SIZE 0x00000008u
#define CYREG_UDB_W32_D0_00 0x400f2080u
#define CYFLD_UDB_W32_D0_0__OFFSET 0x00000000u
#define CYFLD_UDB_W32_D0_0__SIZE 0x00000008u
#define CYFLD_UDB_W32_D0_1__OFFSET 0x00000008u
#define CYFLD_UDB_W32_D0_1__SIZE 0x00000008u
#define CYFLD_UDB_W32_D0_2__OFFSET 0x00000010u
#define CYFLD_UDB_W32_D0_2__SIZE 0x00000008u
#define CYFLD_UDB_W32_D0_3__OFFSET 0x00000018u
#define CYFLD_UDB_W32_D0_3__SIZE 0x00000008u
#define CYREG_UDB_W32_D1_00 0x400f20c0u
#define CYFLD_UDB_W32_D1_0__OFFSET 0x00000000u
#define CYFLD_UDB_W32_D1_0__SIZE 0x00000008u
#define CYFLD_UDB_W32_D1_1__OFFSET 0x00000008u
#define CYFLD_UDB_W32_D1_1__SIZE 0x00000008u
#define CYFLD_UDB_W32_D1_2__OFFSET 0x00000010u
#define CYFLD_UDB_W32_D1_2__SIZE 0x00000008u
#define CYFLD_UDB_W32_D1_3__OFFSET 0x00000018u
#define CYFLD_UDB_W32_D1_3__SIZE 0x00000008u
#define CYREG_UDB_W32_F0_00 0x400f2100u
#define CYFLD_UDB_W32_F0_0__OFFSET 0x00000000u
#define CYFLD_UDB_W32_F0_0__SIZE 0x00000008u
#define CYFLD_UDB_W32_F0_1__OFFSET 0x00000008u
#define CYFLD_UDB_W32_F0_1__SIZE 0x00000008u
#define CYFLD_UDB_W32_F0_2__OFFSET 0x00000010u
#define CYFLD_UDB_W32_F0_2__SIZE 0x00000008u
#define CYFLD_UDB_W32_F0_3__OFFSET 0x00000018u
#define CYFLD_UDB_W32_F0_3__SIZE 0x00000008u
#define CYREG_UDB_W32_F1_00 0x400f2140u
#define CYFLD_UDB_W32_F1_0__OFFSET 0x00000000u
#define CYFLD_UDB_W32_F1_0__SIZE 0x00000008u
#define CYFLD_UDB_W32_F1_1__OFFSET 0x00000008u
#define CYFLD_UDB_W32_F1_1__SIZE 0x00000008u
#define CYFLD_UDB_W32_F1_2__OFFSET 0x00000010u
#define CYFLD_UDB_W32_F1_2__SIZE 0x00000008u
#define CYFLD_UDB_W32_F1_3__OFFSET 0x00000018u
#define CYFLD_UDB_W32_F1_3__SIZE 0x00000008u
#define CYREG_UDB_W32_ST_00 0x400f2180u
#define CYFLD_UDB_W32_ST_0__OFFSET 0x00000000u
#define CYFLD_UDB_W32_ST_0__SIZE 0x00000008u
#define CYFLD_UDB_W32_ST_1__OFFSET 0x00000008u
#define CYFLD_UDB_W32_ST_1__SIZE 0x00000008u
#define CYFLD_UDB_W32_ST_2__OFFSET 0x00000010u
#define CYFLD_UDB_W32_ST_2__SIZE 0x00000008u
#define CYFLD_UDB_W32_ST_3__OFFSET 0x00000018u
#define CYFLD_UDB_W32_ST_3__SIZE 0x00000008u
#define CYREG_UDB_W32_CTL_00 0x400f21c0u
#define CYFLD_UDB_W32_CTL_0__OFFSET 0x00000000u
#define CYFLD_UDB_W32_CTL_0__SIZE 0x00000008u
#define CYFLD_UDB_W32_CTL_1__OFFSET 0x00000008u
#define CYFLD_UDB_W32_CTL_1__SIZE 0x00000008u
#define CYFLD_UDB_W32_CTL_2__OFFSET 0x00000010u
#define CYFLD_UDB_W32_CTL_2__SIZE 0x00000008u
#define CYFLD_UDB_W32_CTL_3__OFFSET 0x00000018u
#define CYFLD_UDB_W32_CTL_3__SIZE 0x00000008u
#define CYREG_UDB_W32_MSK_00 0x400f2200u
#define CYFLD_UDB_W32_MSK_0__OFFSET 0x00000000u
#define CYFLD_UDB_W32_MSK_0__SIZE 0x00000007u
#define CYFLD_UDB_W32_MSK_1__OFFSET 0x00000008u
#define CYFLD_UDB_W32_MSK_1__SIZE 0x00000007u
#define CYFLD_UDB_W32_MSK_2__OFFSET 0x00000010u
#define CYFLD_UDB_W32_MSK_2__SIZE 0x00000007u
#define CYFLD_UDB_W32_MSK_3__OFFSET 0x00000018u
#define CYFLD_UDB_W32_MSK_3__SIZE 0x00000007u
#define CYREG_UDB_W32_ACTL_00 0x400f2240u
#define CYFLD_UDB_W32_FIFO0_CLR_0__OFFSET 0x00000000u
#define CYFLD_UDB_W32_FIFO0_CLR_0__SIZE 0x00000001u
#define CYVAL_UDB_W32_FIFO0_CLR_0_NORMAL 0x00000000u
#define CYVAL_UDB_W32_FIFO0_CLR_0_CLEAR 0x00000001u
#define CYFLD_UDB_W32_FIFO1_CLR_0__OFFSET 0x00000001u
#define CYFLD_UDB_W32_FIFO1_CLR_0__SIZE 0x00000001u
#define CYVAL_UDB_W32_FIFO1_CLR_0_NORMAL 0x00000000u
#define CYVAL_UDB_W32_FIFO1_CLR_0_CLEAR 0x00000001u
#define CYFLD_UDB_W32_FIFO0_LVL_0__OFFSET 0x00000002u
#define CYFLD_UDB_W32_FIFO0_LVL_0__SIZE 0x00000001u
#define CYVAL_UDB_W32_FIFO0_LVL_0_NORMAL 0x00000000u
#define CYVAL_UDB_W32_FIFO0_LVL_0_MID 0x00000001u
#define CYFLD_UDB_W32_FIFO1_LVL_0__OFFSET 0x00000003u
#define CYFLD_UDB_W32_FIFO1_LVL_0__SIZE 0x00000001u
#define CYVAL_UDB_W32_FIFO1_LVL_0_NORMAL 0x00000000u
#define CYVAL_UDB_W32_FIFO1_LVL_0_MID 0x00000001u
#define CYFLD_UDB_W32_INT_EN_0__OFFSET 0x00000004u
#define CYFLD_UDB_W32_INT_EN_0__SIZE 0x00000001u
#define CYVAL_UDB_W32_INT_EN_0_DISABLE 0x00000000u
#define CYVAL_UDB_W32_INT_EN_0_ENABLE 0x00000001u
#define CYFLD_UDB_W32_CNT_START_0__OFFSET 0x00000005u
#define CYFLD_UDB_W32_CNT_START_0__SIZE 0x00000001u
#define CYVAL_UDB_W32_CNT_START_0_DISABLE 0x00000000u
#define CYVAL_UDB_W32_CNT_START_0_ENABLE 0x00000001u
#define CYFLD_UDB_W32_FIFO0_CLR_1__OFFSET 0x00000008u
#define CYFLD_UDB_W32_FIFO0_CLR_1__SIZE 0x00000001u
#define CYVAL_UDB_W32_FIFO0_CLR_1_NORMAL 0x00000000u
#define CYVAL_UDB_W32_FIFO0_CLR_1_CLEAR 0x00000001u
#define CYFLD_UDB_W32_FIFO1_CLR_1__OFFSET 0x00000009u
#define CYFLD_UDB_W32_FIFO1_CLR_1__SIZE 0x00000001u
#define CYVAL_UDB_W32_FIFO1_CLR_1_NORMAL 0x00000000u
#define CYVAL_UDB_W32_FIFO1_CLR_1_CLEAR 0x00000001u
#define CYFLD_UDB_W32_FIFO0_LVL_1__OFFSET 0x0000000au
#define CYFLD_UDB_W32_FIFO0_LVL_1__SIZE 0x00000001u
#define CYVAL_UDB_W32_FIFO0_LVL_1_NORMAL 0x00000000u
#define CYVAL_UDB_W32_FIFO0_LVL_1_MID 0x00000001u
#define CYFLD_UDB_W32_FIFO1_LVL_1__OFFSET 0x0000000bu
#define CYFLD_UDB_W32_FIFO1_LVL_1__SIZE 0x00000001u
#define CYVAL_UDB_W32_FIFO1_LVL_1_NORMAL 0x00000000u
#define CYVAL_UDB_W32_FIFO1_LVL_1_MID 0x00000001u
#define CYFLD_UDB_W32_INT_EN_1__OFFSET 0x0000000cu
#define CYFLD_UDB_W32_INT_EN_1__SIZE 0x00000001u
#define CYVAL_UDB_W32_INT_EN_1_DISABLE 0x00000000u
#define CYVAL_UDB_W32_INT_EN_1_ENABLE 0x00000001u
#define CYFLD_UDB_W32_CNT_START_1__OFFSET 0x0000000du
#define CYFLD_UDB_W32_CNT_START_1__SIZE 0x00000001u
#define CYVAL_UDB_W32_CNT_START_1_DISABLE 0x00000000u
#define CYVAL_UDB_W32_CNT_START_1_ENABLE 0x00000001u
#define CYFLD_UDB_W32_FIFO0_CLR_2__OFFSET 0x00000010u
#define CYFLD_UDB_W32_FIFO0_CLR_2__SIZE 0x00000001u
#define CYVAL_UDB_W32_FIFO0_CLR_2_NORMAL 0x00000000u
#define CYVAL_UDB_W32_FIFO0_CLR_2_CLEAR 0x00000001u
#define CYFLD_UDB_W32_FIFO1_CLR_2__OFFSET 0x00000011u
#define CYFLD_UDB_W32_FIFO1_CLR_2__SIZE 0x00000001u
#define CYVAL_UDB_W32_FIFO1_CLR_2_NORMAL 0x00000000u
#define CYVAL_UDB_W32_FIFO1_CLR_2_CLEAR 0x00000001u
#define CYFLD_UDB_W32_FIFO0_LVL_2__OFFSET 0x00000012u
#define CYFLD_UDB_W32_FIFO0_LVL_2__SIZE 0x00000001u
#define CYVAL_UDB_W32_FIFO0_LVL_2_NORMAL 0x00000000u
#define CYVAL_UDB_W32_FIFO0_LVL_2_MID 0x00000001u
#define CYFLD_UDB_W32_FIFO1_LVL_2__OFFSET 0x00000013u
#define CYFLD_UDB_W32_FIFO1_LVL_2__SIZE 0x00000001u
#define CYVAL_UDB_W32_FIFO1_LVL_2_NORMAL 0x00000000u
#define CYVAL_UDB_W32_FIFO1_LVL_2_MID 0x00000001u
#define CYFLD_UDB_W32_INT_EN_2__OFFSET 0x00000014u
#define CYFLD_UDB_W32_INT_EN_2__SIZE 0x00000001u
#define CYVAL_UDB_W32_INT_EN_2_DISABLE 0x00000000u
#define CYVAL_UDB_W32_INT_EN_2_ENABLE 0x00000001u
#define CYFLD_UDB_W32_CNT_START_2__OFFSET 0x00000015u
#define CYFLD_UDB_W32_CNT_START_2__SIZE 0x00000001u
#define CYVAL_UDB_W32_CNT_START_2_DISABLE 0x00000000u
#define CYVAL_UDB_W32_CNT_START_2_ENABLE 0x00000001u
#define CYFLD_UDB_W32_FIFO0_CLR_3__OFFSET 0x00000018u
#define CYFLD_UDB_W32_FIFO0_CLR_3__SIZE 0x00000001u
#define CYVAL_UDB_W32_FIFO0_CLR_3_NORMAL 0x00000000u
#define CYVAL_UDB_W32_FIFO0_CLR_3_CLEAR 0x00000001u
#define CYFLD_UDB_W32_FIFO1_CLR_3__OFFSET 0x00000019u
#define CYFLD_UDB_W32_FIFO1_CLR_3__SIZE 0x00000001u
#define CYVAL_UDB_W32_FIFO1_CLR_3_NORMAL 0x00000000u
#define CYVAL_UDB_W32_FIFO1_CLR_3_CLEAR 0x00000001u
#define CYFLD_UDB_W32_FIFO0_LVL_3__OFFSET 0x0000001au
#define CYFLD_UDB_W32_FIFO0_LVL_3__SIZE 0x00000001u
#define CYVAL_UDB_W32_FIFO0_LVL_3_NORMAL 0x00000000u
#define CYVAL_UDB_W32_FIFO0_LVL_3_MID 0x00000001u
#define CYFLD_UDB_W32_FIFO1_LVL_3__OFFSET 0x0000001bu
#define CYFLD_UDB_W32_FIFO1_LVL_3__SIZE 0x00000001u
#define CYVAL_UDB_W32_FIFO1_LVL_3_NORMAL 0x00000000u
#define CYVAL_UDB_W32_FIFO1_LVL_3_MID 0x00000001u
#define CYFLD_UDB_W32_INT_EN_3__OFFSET 0x0000001cu
#define CYFLD_UDB_W32_INT_EN_3__SIZE 0x00000001u
#define CYVAL_UDB_W32_INT_EN_3_DISABLE 0x00000000u
#define CYVAL_UDB_W32_INT_EN_3_ENABLE 0x00000001u
#define CYFLD_UDB_W32_CNT_START_3__OFFSET 0x0000001du
#define CYFLD_UDB_W32_CNT_START_3__SIZE 0x00000001u
#define CYVAL_UDB_W32_CNT_START_3_DISABLE 0x00000000u
#define CYVAL_UDB_W32_CNT_START_3_ENABLE 0x00000001u
#define CYREG_UDB_W32_MC_00 0x400f2280u
#define CYFLD_UDB_W32_PLD0_MC_0__OFFSET 0x00000000u
#define CYFLD_UDB_W32_PLD0_MC_0__SIZE 0x00000004u
#define CYFLD_UDB_W32_PLD1_MC_0__OFFSET 0x00000004u
#define CYFLD_UDB_W32_PLD1_MC_0__SIZE 0x00000004u
#define CYFLD_UDB_W32_PLD0_MC_1__OFFSET 0x00000008u
#define CYFLD_UDB_W32_PLD0_MC_1__SIZE 0x00000004u
#define CYFLD_UDB_W32_PLD1_MC_1__OFFSET 0x0000000cu
#define CYFLD_UDB_W32_PLD1_MC_1__SIZE 0x00000004u
#define CYFLD_UDB_W32_PLD0_MC_2__OFFSET 0x00000010u
#define CYFLD_UDB_W32_PLD0_MC_2__SIZE 0x00000004u
#define CYFLD_UDB_W32_PLD1_MC_2__OFFSET 0x00000014u
#define CYFLD_UDB_W32_PLD1_MC_2__SIZE 0x00000004u
#define CYFLD_UDB_W32_PLD0_MC_3__OFFSET 0x00000018u
#define CYFLD_UDB_W32_PLD0_MC_3__SIZE 0x00000004u
#define CYFLD_UDB_W32_PLD1_MC_3__OFFSET 0x0000001cu
#define CYFLD_UDB_W32_PLD1_MC_3__SIZE 0x00000004u
#define CYDEV_UDB_P0_BASE 0x400f3000u
#define CYDEV_UDB_P0_SIZE 0x00000200u
#define CYDEV_UDB_P0_U0_BASE 0x400f3000u
#define CYDEV_UDB_P0_U0_SIZE 0x00000080u
#define CYREG_UDB_P0_U0_PLD_IT0 0x400f3000u
#define CYFLD_UDB_P_U_PLD0_ITxC_0__OFFSET 0x00000000u
#define CYFLD_UDB_P_U_PLD0_ITxC_0__SIZE 0x00000001u
#define CYFLD_UDB_P_U_PLD0_ITxC_1__OFFSET 0x00000001u
#define CYFLD_UDB_P_U_PLD0_ITxC_1__SIZE 0x00000001u
#define CYFLD_UDB_P_U_PLD0_ITxC_2__OFFSET 0x00000002u
#define CYFLD_UDB_P_U_PLD0_ITxC_2__SIZE 0x00000001u
#define CYFLD_UDB_P_U_PLD0_ITxC_3__OFFSET 0x00000003u
#define CYFLD_UDB_P_U_PLD0_ITxC_3__SIZE 0x00000001u
#define CYFLD_UDB_P_U_PLD0_ITxC_4__OFFSET 0x00000004u
#define CYFLD_UDB_P_U_PLD0_ITxC_4__SIZE 0x00000001u
#define CYFLD_UDB_P_U_PLD0_ITxC_5__OFFSET 0x00000005u
#define CYFLD_UDB_P_U_PLD0_ITxC_5__SIZE 0x00000001u
#define CYFLD_UDB_P_U_PLD0_ITxC_6__OFFSET 0x00000006u
#define CYFLD_UDB_P_U_PLD0_ITxC_6__SIZE 0x00000001u
#define CYFLD_UDB_P_U_PLD0_ITxC_7__OFFSET 0x00000007u
#define CYFLD_UDB_P_U_PLD0_ITxC_7__SIZE 0x00000001u
#define CYFLD_UDB_P_U_PLD1_ITxC_0__OFFSET 0x00000008u
#define CYFLD_UDB_P_U_PLD1_ITxC_0__SIZE 0x00000001u
#define CYFLD_UDB_P_U_PLD1_ITxC_1__OFFSET 0x00000009u
#define CYFLD_UDB_P_U_PLD1_ITxC_1__SIZE 0x00000001u
#define CYFLD_UDB_P_U_PLD1_ITxC_2__OFFSET 0x0000000au
#define CYFLD_UDB_P_U_PLD1_ITxC_2__SIZE 0x00000001u
#define CYFLD_UDB_P_U_PLD1_ITxC_3__OFFSET 0x0000000bu
#define CYFLD_UDB_P_U_PLD1_ITxC_3__SIZE 0x00000001u
#define CYFLD_UDB_P_U_PLD1_ITxC_4__OFFSET 0x0000000cu
#define CYFLD_UDB_P_U_PLD1_ITxC_4__SIZE 0x00000001u
#define CYFLD_UDB_P_U_PLD1_ITxC_5__OFFSET 0x0000000du
#define CYFLD_UDB_P_U_PLD1_ITxC_5__SIZE 0x00000001u
#define CYFLD_UDB_P_U_PLD1_ITxC_6__OFFSET 0x0000000eu
#define CYFLD_UDB_P_U_PLD1_ITxC_6__SIZE 0x00000001u
#define CYFLD_UDB_P_U_PLD1_ITxC_7__OFFSET 0x0000000fu
#define CYFLD_UDB_P_U_PLD1_ITxC_7__SIZE 0x00000001u
#define CYFLD_UDB_P_U_PLD0_ITxT_0__OFFSET 0x00000010u
#define CYFLD_UDB_P_U_PLD0_ITxT_0__SIZE 0x00000001u
#define CYFLD_UDB_P_U_PLD0_ITxT_1__OFFSET 0x00000011u
#define CYFLD_UDB_P_U_PLD0_ITxT_1__SIZE 0x00000001u
#define CYFLD_UDB_P_U_PLD0_ITxT_2__OFFSET 0x00000012u
#define CYFLD_UDB_P_U_PLD0_ITxT_2__SIZE 0x00000001u
#define CYFLD_UDB_P_U_PLD0_ITxT_3__OFFSET 0x00000013u
#define CYFLD_UDB_P_U_PLD0_ITxT_3__SIZE 0x00000001u
#define CYFLD_UDB_P_U_PLD0_ITxT_4__OFFSET 0x00000014u
#define CYFLD_UDB_P_U_PLD0_ITxT_4__SIZE 0x00000001u
#define CYFLD_UDB_P_U_PLD0_ITxT_5__OFFSET 0x00000015u
#define CYFLD_UDB_P_U_PLD0_ITxT_5__SIZE 0x00000001u
#define CYFLD_UDB_P_U_PLD0_ITxT_6__OFFSET 0x00000016u
#define CYFLD_UDB_P_U_PLD0_ITxT_6__SIZE 0x00000001u
#define CYFLD_UDB_P_U_PLD0_ITxT_7__OFFSET 0x00000017u
#define CYFLD_UDB_P_U_PLD0_ITxT_7__SIZE 0x00000001u
#define CYFLD_UDB_P_U_PLD1_ITxT_0__OFFSET 0x00000018u
#define CYFLD_UDB_P_U_PLD1_ITxT_0__SIZE 0x00000001u
#define CYFLD_UDB_P_U_PLD1_ITxT_1__OFFSET 0x00000019u
#define CYFLD_UDB_P_U_PLD1_ITxT_1__SIZE 0x00000001u
#define CYFLD_UDB_P_U_PLD1_ITxT_2__OFFSET 0x0000001au
#define CYFLD_UDB_P_U_PLD1_ITxT_2__SIZE 0x00000001u
#define CYFLD_UDB_P_U_PLD1_ITxT_3__OFFSET 0x0000001bu
#define CYFLD_UDB_P_U_PLD1_ITxT_3__SIZE 0x00000001u
#define CYFLD_UDB_P_U_PLD1_ITxT_4__OFFSET 0x0000001cu
#define CYFLD_UDB_P_U_PLD1_ITxT_4__SIZE 0x00000001u
#define CYFLD_UDB_P_U_PLD1_ITxT_5__OFFSET 0x0000001du
#define CYFLD_UDB_P_U_PLD1_ITxT_5__SIZE 0x00000001u
#define CYFLD_UDB_P_U_PLD1_ITxT_6__OFFSET 0x0000001eu
#define CYFLD_UDB_P_U_PLD1_ITxT_6__SIZE 0x00000001u
#define CYFLD_UDB_P_U_PLD1_ITxT_7__OFFSET 0x0000001fu
#define CYFLD_UDB_P_U_PLD1_ITxT_7__SIZE 0x00000001u
#define CYREG_UDB_P0_U0_PLD_IT1 0x400f3004u
#define CYREG_UDB_P0_U0_PLD_IT2 0x400f3008u
#define CYREG_UDB_P0_U0_PLD_IT3 0x400f300cu
#define CYREG_UDB_P0_U0_PLD_IT4 0x400f3010u
#define CYREG_UDB_P0_U0_PLD_IT5 0x400f3014u
#define CYREG_UDB_P0_U0_PLD_IT6 0x400f3018u
#define CYREG_UDB_P0_U0_PLD_IT7 0x400f301cu
#define CYREG_UDB_P0_U0_PLD_IT8 0x400f3020u
#define CYREG_UDB_P0_U0_PLD_IT9 0x400f3024u
#define CYREG_UDB_P0_U0_PLD_IT10 0x400f3028u
#define CYREG_UDB_P0_U0_PLD_IT11 0x400f302cu
#define CYREG_UDB_P0_U0_PLD_ORT0 0x400f3030u
#define CYFLD_UDB_P_U_PLD0_ORT_PTx_0__OFFSET 0x00000000u
#define CYFLD_UDB_P_U_PLD0_ORT_PTx_0__SIZE 0x00000001u
#define CYFLD_UDB_P_U_PLD0_ORT_PTx_1__OFFSET 0x00000001u
#define CYFLD_UDB_P_U_PLD0_ORT_PTx_1__SIZE 0x00000001u
#define CYFLD_UDB_P_U_PLD0_ORT_PTx_2__OFFSET 0x00000002u
#define CYFLD_UDB_P_U_PLD0_ORT_PTx_2__SIZE 0x00000001u
#define CYFLD_UDB_P_U_PLD0_ORT_PTx_3__OFFSET 0x00000003u
#define CYFLD_UDB_P_U_PLD0_ORT_PTx_3__SIZE 0x00000001u
#define CYFLD_UDB_P_U_PLD0_ORT_PTx_4__OFFSET 0x00000004u
#define CYFLD_UDB_P_U_PLD0_ORT_PTx_4__SIZE 0x00000001u
#define CYFLD_UDB_P_U_PLD0_ORT_PTx_5__OFFSET 0x00000005u
#define CYFLD_UDB_P_U_PLD0_ORT_PTx_5__SIZE 0x00000001u
#define CYFLD_UDB_P_U_PLD0_ORT_PTx_6__OFFSET 0x00000006u
#define CYFLD_UDB_P_U_PLD0_ORT_PTx_6__SIZE 0x00000001u
#define CYFLD_UDB_P_U_PLD0_ORT_PTx_7__OFFSET 0x00000007u
#define CYFLD_UDB_P_U_PLD0_ORT_PTx_7__SIZE 0x00000001u
#define CYFLD_UDB_P_U_PLD1_ORT_PTx_0__OFFSET 0x00000008u
#define CYFLD_UDB_P_U_PLD1_ORT_PTx_0__SIZE 0x00000001u
#define CYFLD_UDB_P_U_PLD1_ORT_PTx_1__OFFSET 0x00000009u
#define CYFLD_UDB_P_U_PLD1_ORT_PTx_1__SIZE 0x00000001u
#define CYFLD_UDB_P_U_PLD1_ORT_PTx_2__OFFSET 0x0000000au
#define CYFLD_UDB_P_U_PLD1_ORT_PTx_2__SIZE 0x00000001u
#define CYFLD_UDB_P_U_PLD1_ORT_PTx_3__OFFSET 0x0000000bu
#define CYFLD_UDB_P_U_PLD1_ORT_PTx_3__SIZE 0x00000001u
#define CYFLD_UDB_P_U_PLD1_ORT_PTx_4__OFFSET 0x0000000cu
#define CYFLD_UDB_P_U_PLD1_ORT_PTx_4__SIZE 0x00000001u
#define CYFLD_UDB_P_U_PLD1_ORT_PTx_5__OFFSET 0x0000000du
#define CYFLD_UDB_P_U_PLD1_ORT_PTx_5__SIZE 0x00000001u
#define CYFLD_UDB_P_U_PLD1_ORT_PTx_6__OFFSET 0x0000000eu
#define CYFLD_UDB_P_U_PLD1_ORT_PTx_6__SIZE 0x00000001u
#define CYFLD_UDB_P_U_PLD1_ORT_PTx_7__OFFSET 0x0000000fu
#define CYFLD_UDB_P_U_PLD1_ORT_PTx_7__SIZE 0x00000001u
#define CYREG_UDB_P0_U0_PLD_ORT1 0x400f3032u
#define CYREG_UDB_P0_U0_PLD_ORT2 0x400f3034u
#define CYREG_UDB_P0_U0_PLD_ORT3 0x400f3036u
#define CYREG_UDB_P0_U0_PLD_MC_CFG_CEN_CONST 0x400f3038u
#define CYFLD_UDB_P_U_PLD0_MC0_CEN__OFFSET 0x00000000u
#define CYFLD_UDB_P_U_PLD0_MC0_CEN__SIZE 0x00000001u
#define CYVAL_UDB_P_U_PLD0_MC0_CEN_DISABLE 0x00000000u
#define CYVAL_UDB_P_U_PLD0_MC0_CEN_ENABLE 0x00000001u
#define CYFLD_UDB_P_U_PLD0_MC0_DFF_C__OFFSET 0x00000001u
#define CYFLD_UDB_P_U_PLD0_MC0_DFF_C__SIZE 0x00000001u
#define CYVAL_UDB_P_U_PLD0_MC0_DFF_C_NOINV 0x00000000u
#define CYVAL_UDB_P_U_PLD0_MC0_DFF_C_INVERTED 0x00000001u
#define CYFLD_UDB_P_U_PLD0_MC1_CEN__OFFSET 0x00000002u
#define CYFLD_UDB_P_U_PLD0_MC1_CEN__SIZE 0x00000001u
#define CYVAL_UDB_P_U_PLD0_MC1_CEN_DISABLE 0x00000000u
#define CYVAL_UDB_P_U_PLD0_MC1_CEN_ENABLE 0x00000001u
#define CYFLD_UDB_P_U_PLD0_MC1_DFF_C__OFFSET 0x00000003u
#define CYFLD_UDB_P_U_PLD0_MC1_DFF_C__SIZE 0x00000001u
#define CYVAL_UDB_P_U_PLD0_MC1_DFF_C_NOINV 0x00000000u
#define CYVAL_UDB_P_U_PLD0_MC1_DFF_C_INVERTED 0x00000001u
#define CYFLD_UDB_P_U_PLD0_MC2_CEN__OFFSET 0x00000004u
#define CYFLD_UDB_P_U_PLD0_MC2_CEN__SIZE 0x00000001u
#define CYVAL_UDB_P_U_PLD0_MC2_CEN_DISABLE 0x00000000u
#define CYVAL_UDB_P_U_PLD0_MC2_CEN_ENABLE 0x00000001u
#define CYFLD_UDB_P_U_PLD0_MC2_DFF_C__OFFSET 0x00000005u
#define CYFLD_UDB_P_U_PLD0_MC2_DFF_C__SIZE 0x00000001u
#define CYVAL_UDB_P_U_PLD0_MC2_DFF_C_NOINV 0x00000000u
#define CYVAL_UDB_P_U_PLD0_MC2_DFF_C_INVERTED 0x00000001u
#define CYFLD_UDB_P_U_PLD0_MC3_CEN__OFFSET 0x00000006u
#define CYFLD_UDB_P_U_PLD0_MC3_CEN__SIZE 0x00000001u
#define CYVAL_UDB_P_U_PLD0_MC3_CEN_DISABLE 0x00000000u
#define CYVAL_UDB_P_U_PLD0_MC3_CEN_ENABLE 0x00000001u
#define CYFLD_UDB_P_U_PLD0_MC3_DFF_C__OFFSET 0x00000007u
#define CYFLD_UDB_P_U_PLD0_MC3_DFF_C__SIZE 0x00000001u
#define CYVAL_UDB_P_U_PLD0_MC3_DFF_C_NOINV 0x00000000u
#define CYVAL_UDB_P_U_PLD0_MC3_DFF_C_INVERTED 0x00000001u
#define CYFLD_UDB_P_U_PLD1_MC0_CEN__OFFSET 0x00000008u
#define CYFLD_UDB_P_U_PLD1_MC0_CEN__SIZE 0x00000001u
#define CYVAL_UDB_P_U_PLD1_MC0_CEN_DISABLE 0x00000000u
#define CYVAL_UDB_P_U_PLD1_MC0_CEN_ENABLE 0x00000001u
#define CYFLD_UDB_P_U_PLD1_MC0_DFF_C__OFFSET 0x00000009u
#define CYFLD_UDB_P_U_PLD1_MC0_DFF_C__SIZE 0x00000001u
#define CYVAL_UDB_P_U_PLD1_MC0_DFF_C_NOINV 0x00000000u
#define CYVAL_UDB_P_U_PLD1_MC0_DFF_C_INVERTED 0x00000001u
#define CYFLD_UDB_P_U_PLD1_MC1_CEN__OFFSET 0x0000000au
#define CYFLD_UDB_P_U_PLD1_MC1_CEN__SIZE 0x00000001u
#define CYVAL_UDB_P_U_PLD1_MC1_CEN_DISABLE 0x00000000u
#define CYVAL_UDB_P_U_PLD1_MC1_CEN_ENABLE 0x00000001u
#define CYFLD_UDB_P_U_PLD1_MC1_DFF_C__OFFSET 0x0000000bu
#define CYFLD_UDB_P_U_PLD1_MC1_DFF_C__SIZE 0x00000001u
#define CYVAL_UDB_P_U_PLD1_MC1_DFF_C_NOINV 0x00000000u
#define CYVAL_UDB_P_U_PLD1_MC1_DFF_C_INVERTED 0x00000001u
#define CYFLD_UDB_P_U_PLD1_MC2_CEN__OFFSET 0x0000000cu
#define CYFLD_UDB_P_U_PLD1_MC2_CEN__SIZE 0x00000001u
#define CYVAL_UDB_P_U_PLD1_MC2_CEN_DISABLE 0x00000000u
#define CYVAL_UDB_P_U_PLD1_MC2_CEN_ENABLE 0x00000001u
#define CYFLD_UDB_P_U_PLD1_MC2_DFF_C__OFFSET 0x0000000du
#define CYFLD_UDB_P_U_PLD1_MC2_DFF_C__SIZE 0x00000001u
#define CYVAL_UDB_P_U_PLD1_MC2_DFF_C_NOINV 0x00000000u
#define CYVAL_UDB_P_U_PLD1_MC2_DFF_C_INVERTED 0x00000001u
#define CYFLD_UDB_P_U_PLD1_MC3_CEN__OFFSET 0x0000000eu
#define CYFLD_UDB_P_U_PLD1_MC3_CEN__SIZE 0x00000001u
#define CYVAL_UDB_P_U_PLD1_MC3_CEN_DISABLE 0x00000000u
#define CYVAL_UDB_P_U_PLD1_MC3_CEN_ENABLE 0x00000001u
#define CYFLD_UDB_P_U_PLD1_MC3_DFF_C__OFFSET 0x0000000fu
#define CYFLD_UDB_P_U_PLD1_MC3_DFF_C__SIZE 0x00000001u
#define CYVAL_UDB_P_U_PLD1_MC3_DFF_C_NOINV 0x00000000u
#define CYVAL_UDB_P_U_PLD1_MC3_DFF_C_INVERTED 0x00000001u
#define CYREG_UDB_P0_U0_PLD_MC_CFG_XORFB 0x400f303au
#define CYFLD_UDB_P_U_PLD0_MC0_XORFB__OFFSET 0x00000000u
#define CYFLD_UDB_P_U_PLD0_MC0_XORFB__SIZE 0x00000002u
#define CYVAL_UDB_P_U_PLD0_MC0_XORFB_DFF 0x00000000u
#define CYVAL_UDB_P_U_PLD0_MC0_XORFB_CARRY 0x00000001u
#define CYVAL_UDB_P_U_PLD0_MC0_XORFB_TFF_H 0x00000002u
#define CYVAL_UDB_P_U_PLD0_MC0_XORFB_TFF_L 0x00000003u
#define CYFLD_UDB_P_U_PLD0_MC1_XORFB__OFFSET 0x00000002u
#define CYFLD_UDB_P_U_PLD0_MC1_XORFB__SIZE 0x00000002u
#define CYVAL_UDB_P_U_PLD0_MC1_XORFB_DFF 0x00000000u
#define CYVAL_UDB_P_U_PLD0_MC1_XORFB_CARRY 0x00000001u
#define CYVAL_UDB_P_U_PLD0_MC1_XORFB_TFF_H 0x00000002u
#define CYVAL_UDB_P_U_PLD0_MC1_XORFB_TFF_L 0x00000003u
#define CYFLD_UDB_P_U_PLD0_MC2_XORFB__OFFSET 0x00000004u
#define CYFLD_UDB_P_U_PLD0_MC2_XORFB__SIZE 0x00000002u
#define CYVAL_UDB_P_U_PLD0_MC2_XORFB_DFF 0x00000000u
#define CYVAL_UDB_P_U_PLD0_MC2_XORFB_CARRY 0x00000001u
#define CYVAL_UDB_P_U_PLD0_MC2_XORFB_TFF_H 0x00000002u
#define CYVAL_UDB_P_U_PLD0_MC2_XORFB_TFF_L 0x00000003u
#define CYFLD_UDB_P_U_PLD0_MC3_XORFB__OFFSET 0x00000006u
#define CYFLD_UDB_P_U_PLD0_MC3_XORFB__SIZE 0x00000002u
#define CYVAL_UDB_P_U_PLD0_MC3_XORFB_DFF 0x00000000u
#define CYVAL_UDB_P_U_PLD0_MC3_XORFB_CARRY 0x00000001u
#define CYVAL_UDB_P_U_PLD0_MC3_XORFB_TFF_H 0x00000002u
#define CYVAL_UDB_P_U_PLD0_MC3_XORFB_TFF_L 0x00000003u
#define CYFLD_UDB_P_U_PLD1_MC0_XORFB__OFFSET 0x00000008u
#define CYFLD_UDB_P_U_PLD1_MC0_XORFB__SIZE 0x00000002u
#define CYVAL_UDB_P_U_PLD1_MC0_XORFB_DFF 0x00000000u
#define CYVAL_UDB_P_U_PLD1_MC0_XORFB_CARRY 0x00000001u
#define CYVAL_UDB_P_U_PLD1_MC0_XORFB_TFF_H 0x00000002u
#define CYVAL_UDB_P_U_PLD1_MC0_XORFB_TFF_L 0x00000003u
#define CYFLD_UDB_P_U_PLD1_MC1_XORFB__OFFSET 0x0000000au
#define CYFLD_UDB_P_U_PLD1_MC1_XORFB__SIZE 0x00000002u
#define CYVAL_UDB_P_U_PLD1_MC1_XORFB_DFF 0x00000000u
#define CYVAL_UDB_P_U_PLD1_MC1_XORFB_CARRY 0x00000001u
#define CYVAL_UDB_P_U_PLD1_MC1_XORFB_TFF_H 0x00000002u
#define CYVAL_UDB_P_U_PLD1_MC1_XORFB_TFF_L 0x00000003u
#define CYFLD_UDB_P_U_PLD1_MC2_XORFB__OFFSET 0x0000000cu
#define CYFLD_UDB_P_U_PLD1_MC2_XORFB__SIZE 0x00000002u
#define CYVAL_UDB_P_U_PLD1_MC2_XORFB_DFF 0x00000000u
#define CYVAL_UDB_P_U_PLD1_MC2_XORFB_CARRY 0x00000001u
#define CYVAL_UDB_P_U_PLD1_MC2_XORFB_TFF_H 0x00000002u
#define CYVAL_UDB_P_U_PLD1_MC2_XORFB_TFF_L 0x00000003u
#define CYFLD_UDB_P_U_PLD1_MC3_XORFB__OFFSET 0x0000000eu
#define CYFLD_UDB_P_U_PLD1_MC3_XORFB__SIZE 0x00000002u
#define CYVAL_UDB_P_U_PLD1_MC3_XORFB_DFF 0x00000000u
#define CYVAL_UDB_P_U_PLD1_MC3_XORFB_CARRY 0x00000001u
#define CYVAL_UDB_P_U_PLD1_MC3_XORFB_TFF_H 0x00000002u
#define CYVAL_UDB_P_U_PLD1_MC3_XORFB_TFF_L 0x00000003u
#define CYREG_UDB_P0_U0_PLD_MC_SET_RESET 0x400f303cu
#define CYFLD_UDB_P_U_PLD0_MC0_SET_SEL__OFFSET 0x00000000u
#define CYFLD_UDB_P_U_PLD0_MC0_SET_SEL__SIZE 0x00000001u
#define CYVAL_UDB_P_U_PLD0_MC0_SET_SEL_DISABLE 0x00000000u
#define CYVAL_UDB_P_U_PLD0_MC0_SET_SEL_ENABLE 0x00000001u
#define CYFLD_UDB_P_U_PLD0_MC0_RESET_SEL__OFFSET 0x00000001u
#define CYFLD_UDB_P_U_PLD0_MC0_RESET_SEL__SIZE 0x00000001u
#define CYVAL_UDB_P_U_PLD0_MC0_RESET_SEL_DISABLE 0x00000000u
#define CYVAL_UDB_P_U_PLD0_MC0_RESET_SEL_ENABLE 0x00000001u
#define CYFLD_UDB_P_U_PLD0_MC1_SET_SEL__OFFSET 0x00000002u
#define CYFLD_UDB_P_U_PLD0_MC1_SET_SEL__SIZE 0x00000001u
#define CYVAL_UDB_P_U_PLD0_MC1_SET_SEL_DISABLE 0x00000000u
#define CYVAL_UDB_P_U_PLD0_MC1_SET_SEL_ENABLE 0x00000001u
#define CYFLD_UDB_P_U_PLD0_MC1_RESET_SEL__OFFSET 0x00000003u
#define CYFLD_UDB_P_U_PLD0_MC1_RESET_SEL__SIZE 0x00000001u
#define CYVAL_UDB_P_U_PLD0_MC1_RESET_SEL_DISABLE 0x00000000u
#define CYVAL_UDB_P_U_PLD0_MC1_RESET_SEL_ENABLE 0x00000001u
#define CYFLD_UDB_P_U_PLD0_MC2_SET_SEL__OFFSET 0x00000004u
#define CYFLD_UDB_P_U_PLD0_MC2_SET_SEL__SIZE 0x00000001u
#define CYVAL_UDB_P_U_PLD0_MC2_SET_SEL_DISABLE 0x00000000u
#define CYVAL_UDB_P_U_PLD0_MC2_SET_SEL_ENABLE 0x00000001u
#define CYFLD_UDB_P_U_PLD0_MC2_RESET_SEL__OFFSET 0x00000005u
#define CYFLD_UDB_P_U_PLD0_MC2_RESET_SEL__SIZE 0x00000001u
#define CYVAL_UDB_P_U_PLD0_MC2_RESET_SEL_DISABLE 0x00000000u
#define CYVAL_UDB_P_U_PLD0_MC2_RESET_SEL_ENABLE 0x00000001u
#define CYFLD_UDB_P_U_PLD0_MC3_SET_SEL__OFFSET 0x00000006u
#define CYFLD_UDB_P_U_PLD0_MC3_SET_SEL__SIZE 0x00000001u
#define CYVAL_UDB_P_U_PLD0_MC3_SET_SEL_DISABLE 0x00000000u
#define CYVAL_UDB_P_U_PLD0_MC3_SET_SEL_ENABLE 0x00000001u
#define CYFLD_UDB_P_U_PLD0_MC3_RESET_SEL__OFFSET 0x00000007u
#define CYFLD_UDB_P_U_PLD0_MC3_RESET_SEL__SIZE 0x00000001u
#define CYVAL_UDB_P_U_PLD0_MC3_RESET_SEL_DISABLE 0x00000000u
#define CYVAL_UDB_P_U_PLD0_MC3_RESET_SEL_ENABLE 0x00000001u
#define CYFLD_UDB_P_U_PLD1_MC0_SET_SEL__OFFSET 0x00000008u
#define CYFLD_UDB_P_U_PLD1_MC0_SET_SEL__SIZE 0x00000001u
#define CYVAL_UDB_P_U_PLD1_MC0_SET_SEL_DISABLE 0x00000000u
#define CYVAL_UDB_P_U_PLD1_MC0_SET_SEL_ENABLE 0x00000001u
#define CYFLD_UDB_P_U_PLD1_MC0_RESET_SEL__OFFSET 0x00000009u
#define CYFLD_UDB_P_U_PLD1_MC0_RESET_SEL__SIZE 0x00000001u
#define CYVAL_UDB_P_U_PLD1_MC0_RESET_SEL_DISABLE 0x00000000u
#define CYVAL_UDB_P_U_PLD1_MC0_RESET_SEL_ENABLE 0x00000001u
#define CYFLD_UDB_P_U_PLD1_MC1_SET_SEL__OFFSET 0x0000000au
#define CYFLD_UDB_P_U_PLD1_MC1_SET_SEL__SIZE 0x00000001u
#define CYVAL_UDB_P_U_PLD1_MC1_SET_SEL_DISABLE 0x00000000u
#define CYVAL_UDB_P_U_PLD1_MC1_SET_SEL_ENABLE 0x00000001u
#define CYFLD_UDB_P_U_PLD1_MC1_RESET_SEL__OFFSET 0x0000000bu
#define CYFLD_UDB_P_U_PLD1_MC1_RESET_SEL__SIZE 0x00000001u
#define CYVAL_UDB_P_U_PLD1_MC1_RESET_SEL_DISABLE 0x00000000u
#define CYVAL_UDB_P_U_PLD1_MC1_RESET_SEL_ENABLE 0x00000001u
#define CYFLD_UDB_P_U_PLD1_MC2_SET_SEL__OFFSET 0x0000000cu
#define CYFLD_UDB_P_U_PLD1_MC2_SET_SEL__SIZE 0x00000001u
#define CYVAL_UDB_P_U_PLD1_MC2_SET_SEL_DISABLE 0x00000000u
#define CYVAL_UDB_P_U_PLD1_MC2_SET_SEL_ENABLE 0x00000001u
#define CYFLD_UDB_P_U_PLD1_MC2_RESET_SEL__OFFSET 0x0000000du
#define CYFLD_UDB_P_U_PLD1_MC2_RESET_SEL__SIZE 0x00000001u
#define CYVAL_UDB_P_U_PLD1_MC2_RESET_SEL_DISABLE 0x00000000u
#define CYVAL_UDB_P_U_PLD1_MC2_RESET_SEL_ENABLE 0x00000001u
#define CYFLD_UDB_P_U_PLD1_MC3_SET_SEL__OFFSET 0x0000000eu
#define CYFLD_UDB_P_U_PLD1_MC3_SET_SEL__SIZE 0x00000001u
#define CYVAL_UDB_P_U_PLD1_MC3_SET_SEL_DISABLE 0x00000000u
#define CYVAL_UDB_P_U_PLD1_MC3_SET_SEL_ENABLE 0x00000001u
#define CYFLD_UDB_P_U_PLD1_MC3_RESET_SEL__OFFSET 0x0000000fu
#define CYFLD_UDB_P_U_PLD1_MC3_RESET_SEL__SIZE 0x00000001u
#define CYVAL_UDB_P_U_PLD1_MC3_RESET_SEL_DISABLE 0x00000000u
#define CYVAL_UDB_P_U_PLD1_MC3_RESET_SEL_ENABLE 0x00000001u
#define CYREG_UDB_P0_U0_PLD_MC_CFG_BYPASS 0x400f303eu
#define CYFLD_UDB_P_U_PLD0_MC0_BYPASS__OFFSET 0x00000000u
#define CYFLD_UDB_P_U_PLD0_MC0_BYPASS__SIZE 0x00000001u
#define CYVAL_UDB_P_U_PLD0_MC0_BYPASS_REGISTER 0x00000000u
#define CYVAL_UDB_P_U_PLD0_MC0_BYPASS_COMBINATIONAL 0x00000001u
#define CYFLD_UDB_P_U_NC1__OFFSET 0x00000001u
#define CYFLD_UDB_P_U_NC1__SIZE 0x00000001u
#define CYFLD_UDB_P_U_PLD0_MC1_BYPASS__OFFSET 0x00000002u
#define CYFLD_UDB_P_U_PLD0_MC1_BYPASS__SIZE 0x00000001u
#define CYVAL_UDB_P_U_PLD0_MC1_BYPASS_REGISTER 0x00000000u
#define CYVAL_UDB_P_U_PLD0_MC1_BYPASS_COMBINATIONAL 0x00000001u
#define CYFLD_UDB_P_U_NC3__OFFSET 0x00000003u
#define CYFLD_UDB_P_U_NC3__SIZE 0x00000001u
#define CYFLD_UDB_P_U_PLD0_MC2_BYPASS__OFFSET 0x00000004u
#define CYFLD_UDB_P_U_PLD0_MC2_BYPASS__SIZE 0x00000001u
#define CYVAL_UDB_P_U_PLD0_MC2_BYPASS_REGISTER 0x00000000u
#define CYVAL_UDB_P_U_PLD0_MC2_BYPASS_COMBINATIONAL 0x00000001u
#define CYFLD_UDB_P_U_NC5__OFFSET 0x00000005u
#define CYFLD_UDB_P_U_NC5__SIZE 0x00000001u
#define CYFLD_UDB_P_U_PLD0_MC3_BYPASS__OFFSET 0x00000006u
#define CYFLD_UDB_P_U_PLD0_MC3_BYPASS__SIZE 0x00000001u
#define CYVAL_UDB_P_U_PLD0_MC3_BYPASS_REGISTER 0x00000000u
#define CYVAL_UDB_P_U_PLD0_MC3_BYPASS_COMBINATIONAL 0x00000001u
#define CYFLD_UDB_P_U_NC7__OFFSET 0x00000007u
#define CYFLD_UDB_P_U_NC7__SIZE 0x00000001u
#define CYFLD_UDB_P_U_PLD1_MC0_BYPASS__OFFSET 0x00000008u
#define CYFLD_UDB_P_U_PLD1_MC0_BYPASS__SIZE 0x00000001u
#define CYVAL_UDB_P_U_PLD1_MC0_BYPASS_REGISTER 0x00000000u
#define CYVAL_UDB_P_U_PLD1_MC0_BYPASS_COMBINATIONAL 0x00000001u
#define CYFLD_UDB_P_U_NC9__OFFSET 0x00000009u
#define CYFLD_UDB_P_U_NC9__SIZE 0x00000001u
#define CYFLD_UDB_P_U_PLD1_MC1_BYPASS__OFFSET 0x0000000au
#define CYFLD_UDB_P_U_PLD1_MC1_BYPASS__SIZE 0x00000001u
#define CYVAL_UDB_P_U_PLD1_MC1_BYPASS_REGISTER 0x00000000u
#define CYVAL_UDB_P_U_PLD1_MC1_BYPASS_COMBINATIONAL 0x00000001u
#define CYFLD_UDB_P_U_NC11__OFFSET 0x0000000bu
#define CYFLD_UDB_P_U_NC11__SIZE 0x00000001u
#define CYFLD_UDB_P_U_PLD1_MC2_BYPASS__OFFSET 0x0000000cu
#define CYFLD_UDB_P_U_PLD1_MC2_BYPASS__SIZE 0x00000001u
#define CYVAL_UDB_P_U_PLD1_MC2_BYPASS_REGISTER 0x00000000u
#define CYVAL_UDB_P_U_PLD1_MC2_BYPASS_COMBINATIONAL 0x00000001u
#define CYFLD_UDB_P_U_NC13__OFFSET 0x0000000du
#define CYFLD_UDB_P_U_NC13__SIZE 0x00000001u
#define CYFLD_UDB_P_U_PLD1_MC3_BYPASS__OFFSET 0x0000000eu
#define CYFLD_UDB_P_U_PLD1_MC3_BYPASS__SIZE 0x00000001u
#define CYVAL_UDB_P_U_PLD1_MC3_BYPASS_REGISTER 0x00000000u
#define CYVAL_UDB_P_U_PLD1_MC3_BYPASS_COMBINATIONAL 0x00000001u
#define CYFLD_UDB_P_U_NC15__OFFSET 0x0000000fu
#define CYFLD_UDB_P_U_NC15__SIZE 0x00000001u
#define CYREG_UDB_P0_U0_CFG0 0x400f3040u
#define CYFLD_UDB_P_U_RAD0__OFFSET 0x00000000u
#define CYFLD_UDB_P_U_RAD0__SIZE 0x00000003u
#define CYVAL_UDB_P_U_RAD0_OFF 0x00000000u
#define CYVAL_UDB_P_U_RAD0_DP_IN0 0x00000001u
#define CYVAL_UDB_P_U_RAD0_DP_IN1 0x00000002u
#define CYVAL_UDB_P_U_RAD0_DP_IN2 0x00000003u
#define CYVAL_UDB_P_U_RAD0_DP_IN3 0x00000004u
#define CYVAL_UDB_P_U_RAD0_DP_IN4 0x00000005u
#define CYVAL_UDB_P_U_RAD0_DP_IN5 0x00000006u
#define CYVAL_UDB_P_U_RAD0_RESERVED 0x00000007u
#define CYFLD_UDB_P_U_RAD1__OFFSET 0x00000004u
#define CYFLD_UDB_P_U_RAD1__SIZE 0x00000003u
#define CYVAL_UDB_P_U_RAD1_OFF 0x00000000u
#define CYVAL_UDB_P_U_RAD1_DP_IN0 0x00000001u
#define CYVAL_UDB_P_U_RAD1_DP_IN1 0x00000002u
#define CYVAL_UDB_P_U_RAD1_DP_IN2 0x00000003u
#define CYVAL_UDB_P_U_RAD1_DP_IN3 0x00000004u
#define CYVAL_UDB_P_U_RAD1_DP_IN4 0x00000005u
#define CYVAL_UDB_P_U_RAD1_DP_IN5 0x00000006u
#define CYVAL_UDB_P_U_RAD1_RESERVED 0x00000007u
#define CYREG_UDB_P0_U0_CFG1 0x400f3041u
#define CYFLD_UDB_P_U_RAD2__OFFSET 0x00000000u
#define CYFLD_UDB_P_U_RAD2__SIZE 0x00000003u
#define CYVAL_UDB_P_U_RAD2_OFF 0x00000000u
#define CYVAL_UDB_P_U_RAD2_DP_IN0 0x00000001u
#define CYVAL_UDB_P_U_RAD2_DP_IN1 0x00000002u
#define CYVAL_UDB_P_U_RAD2_DP_IN2 0x00000003u
#define CYVAL_UDB_P_U_RAD2_DP_IN3 0x00000004u
#define CYVAL_UDB_P_U_RAD2_DP_IN4 0x00000005u
#define CYVAL_UDB_P_U_RAD2_DP_IN5 0x00000006u
#define CYVAL_UDB_P_U_RAD2_RESERVED 0x00000007u
#define CYFLD_UDB_P_U_DP_RTE_BYPASS0__OFFSET 0x00000003u
#define CYFLD_UDB_P_U_DP_RTE_BYPASS0__SIZE 0x00000001u
#define CYVAL_UDB_P_U_DP_RTE_BYPASS0_DP_IN0_ROUTE 0x00000000u
#define CYVAL_UDB_P_U_DP_RTE_BYPASS0_DP_IN0_BYPASS 0x00000001u
#define CYFLD_UDB_P_U_DP_RTE_BYPASS1__OFFSET 0x00000004u
#define CYFLD_UDB_P_U_DP_RTE_BYPASS1__SIZE 0x00000001u
#define CYVAL_UDB_P_U_DP_RTE_BYPASS1_DP_IN1_ROUTE 0x00000000u
#define CYVAL_UDB_P_U_DP_RTE_BYPASS1_DP_IN1_BYPASS 0x00000001u
#define CYFLD_UDB_P_U_DP_RTE_BYPASS2__OFFSET 0x00000005u
#define CYFLD_UDB_P_U_DP_RTE_BYPASS2__SIZE 0x00000001u
#define CYVAL_UDB_P_U_DP_RTE_BYPASS2_DP_IN2_ROUTE 0x00000000u
#define CYVAL_UDB_P_U_DP_RTE_BYPASS2_DP_IN2_BYPASS 0x00000001u
#define CYFLD_UDB_P_U_DP_RTE_BYPASS3__OFFSET 0x00000006u
#define CYFLD_UDB_P_U_DP_RTE_BYPASS3__SIZE 0x00000001u
#define CYVAL_UDB_P_U_DP_RTE_BYPASS3_DP_IN3_ROUTE 0x00000000u
#define CYVAL_UDB_P_U_DP_RTE_BYPASS3_DP_IN3_BYPASS 0x00000001u
#define CYFLD_UDB_P_U_DP_RTE_BYPASS4__OFFSET 0x00000007u
#define CYFLD_UDB_P_U_DP_RTE_BYPASS4__SIZE 0x00000001u
#define CYVAL_UDB_P_U_DP_RTE_BYPASS4_DP_IN4_ROUTE 0x00000000u
#define CYVAL_UDB_P_U_DP_RTE_BYPASS4_DP_IN4_BYPASS 0x00000001u
#define CYREG_UDB_P0_U0_CFG2 0x400f3042u
#define CYFLD_UDB_P_U_F0_LD__OFFSET 0x00000000u
#define CYFLD_UDB_P_U_F0_LD__SIZE 0x00000003u
#define CYVAL_UDB_P_U_F0_LD_OFF 0x00000000u
#define CYVAL_UDB_P_U_F0_LD_DP_IN0 0x00000001u
#define CYVAL_UDB_P_U_F0_LD_DP_IN1 0x00000002u
#define CYVAL_UDB_P_U_F0_LD_DP_IN2 0x00000003u
#define CYVAL_UDB_P_U_F0_LD_DP_IN3 0x00000004u
#define CYVAL_UDB_P_U_F0_LD_DP_IN4 0x00000005u
#define CYVAL_UDB_P_U_F0_LD_DP_IN5 0x00000006u
#define CYVAL_UDB_P_U_F0_LD_RESERVED 0x00000007u
#define CYFLD_UDB_P_U_DP_RTE_BYPASS5__OFFSET 0x00000003u
#define CYFLD_UDB_P_U_DP_RTE_BYPASS5__SIZE 0x00000001u
#define CYVAL_UDB_P_U_DP_RTE_BYPASS5_DP_IN5_ROUTE 0x00000000u
#define CYVAL_UDB_P_U_DP_RTE_BYPASS5_DP_IN5_BYPASS 0x00000001u
#define CYFLD_UDB_P_U_F1_LD__OFFSET 0x00000004u
#define CYFLD_UDB_P_U_F1_LD__SIZE 0x00000003u
#define CYVAL_UDB_P_U_F1_LD_OFF 0x00000000u
#define CYVAL_UDB_P_U_F1_LD_DP_IN0 0x00000001u
#define CYVAL_UDB_P_U_F1_LD_DP_IN1 0x00000002u
#define CYVAL_UDB_P_U_F1_LD_DP_IN2 0x00000003u
#define CYVAL_UDB_P_U_F1_LD_DP_IN3 0x00000004u
#define CYVAL_UDB_P_U_F1_LD_DP_IN4 0x00000005u
#define CYVAL_UDB_P_U_F1_LD_DP_IN5 0x00000006u
#define CYVAL_UDB_P_U_F1_LD_RESERVED 0x00000007u
#define CYREG_UDB_P0_U0_CFG3 0x400f3043u
#define CYFLD_UDB_P_U_D0_LD__OFFSET 0x00000000u
#define CYFLD_UDB_P_U_D0_LD__SIZE 0x00000003u
#define CYVAL_UDB_P_U_D0_LD_OFF 0x00000000u
#define CYVAL_UDB_P_U_D0_LD_DP_IN0 0x00000001u
#define CYVAL_UDB_P_U_D0_LD_DP_IN1 0x00000002u
#define CYVAL_UDB_P_U_D0_LD_DP_IN2 0x00000003u
#define CYVAL_UDB_P_U_D0_LD_DP_IN3 0x00000004u
#define CYVAL_UDB_P_U_D0_LD_DP_IN4 0x00000005u
#define CYVAL_UDB_P_U_D0_LD_DP_IN5 0x00000006u
#define CYVAL_UDB_P_U_D0_LD_RESERVED 0x00000007u
#define CYFLD_UDB_P_U_D1_LD__OFFSET 0x00000004u
#define CYFLD_UDB_P_U_D1_LD__SIZE 0x00000003u
#define CYVAL_UDB_P_U_D1_LD_OFF 0x00000000u
#define CYVAL_UDB_P_U_D1_LD_DP_IN0 0x00000001u
#define CYVAL_UDB_P_U_D1_LD_DP_IN1 0x00000002u
#define CYVAL_UDB_P_U_D1_LD_DP_IN2 0x00000003u
#define CYVAL_UDB_P_U_D1_LD_DP_IN3 0x00000004u
#define CYVAL_UDB_P_U_D1_LD_DP_IN4 0x00000005u
#define CYVAL_UDB_P_U_D1_LD_DP_IN5 0x00000006u
#define CYVAL_UDB_P_U_D1_LD_RESERVED 0x00000007u
#define CYREG_UDB_P0_U0_CFG4 0x400f3044u
#define CYFLD_UDB_P_U_SI_MUX__OFFSET 0x00000000u
#define CYFLD_UDB_P_U_SI_MUX__SIZE 0x00000003u
#define CYVAL_UDB_P_U_SI_MUX_OFF 0x00000000u
#define CYVAL_UDB_P_U_SI_MUX_DP_IN0 0x00000001u
#define CYVAL_UDB_P_U_SI_MUX_DP_IN1 0x00000002u
#define CYVAL_UDB_P_U_SI_MUX_DP_IN2 0x00000003u
#define CYVAL_UDB_P_U_SI_MUX_DP_IN3 0x00000004u
#define CYVAL_UDB_P_U_SI_MUX_DP_IN4 0x00000005u
#define CYVAL_UDB_P_U_SI_MUX_DP_IN5 0x00000006u
#define CYVAL_UDB_P_U_SI_MUX_RESERVED 0x00000007u
#define CYFLD_UDB_P_U_CI_MUX__OFFSET 0x00000004u
#define CYFLD_UDB_P_U_CI_MUX__SIZE 0x00000003u
#define CYVAL_UDB_P_U_CI_MUX_OFF 0x00000000u
#define CYVAL_UDB_P_U_CI_MUX_DP_IN0 0x00000001u
#define CYVAL_UDB_P_U_CI_MUX_DP_IN1 0x00000002u
#define CYVAL_UDB_P_U_CI_MUX_DP_IN2 0x00000003u
#define CYVAL_UDB_P_U_CI_MUX_DP_IN3 0x00000004u
#define CYVAL_UDB_P_U_CI_MUX_DP_IN4 0x00000005u
#define CYVAL_UDB_P_U_CI_MUX_DP_IN5 0x00000006u
#define CYVAL_UDB_P_U_CI_MUX_RESERVED 0x00000007u
#define CYREG_UDB_P0_U0_CFG5 0x400f3045u
#define CYFLD_UDB_P_U_OUT0__OFFSET 0x00000000u
#define CYFLD_UDB_P_U_OUT0__SIZE 0x00000004u
#define CYVAL_UDB_P_U_OUT0_CE0 0x00000000u
#define CYVAL_UDB_P_U_OUT0_CL0 0x00000001u
#define CYVAL_UDB_P_U_OUT0_Z0 0x00000002u
#define CYVAL_UDB_P_U_OUT0_FF0 0x00000003u
#define CYVAL_UDB_P_U_OUT0_CE1 0x00000004u
#define CYVAL_UDB_P_U_OUT0_CL1 0x00000005u
#define CYVAL_UDB_P_U_OUT0_Z1 0x00000006u
#define CYVAL_UDB_P_U_OUT0_FF1 0x00000007u
#define CYVAL_UDB_P_U_OUT0_OV_MSB 0x00000008u
#define CYVAL_UDB_P_U_OUT0_CO_MSB 0x00000009u
#define CYVAL_UDB_P_U_OUT0_CMSBO 0x0000000au
#define CYVAL_UDB_P_U_OUT0_SO 0x0000000bu
#define CYVAL_UDB_P_U_OUT0_F0_BLK_STAT 0x0000000cu
#define CYVAL_UDB_P_U_OUT0_F1_BLK_STAT 0x0000000du
#define CYVAL_UDB_P_U_OUT0_F0_BUS_STAT 0x0000000eu
#define CYVAL_UDB_P_U_OUT0_F1_BUS_STAT 0x0000000fu
#define CYFLD_UDB_P_U_OUT1__OFFSET 0x00000004u
#define CYFLD_UDB_P_U_OUT1__SIZE 0x00000004u
#define CYVAL_UDB_P_U_OUT1_CE0 0x00000000u
#define CYVAL_UDB_P_U_OUT1_CL0 0x00000001u
#define CYVAL_UDB_P_U_OUT1_Z0 0x00000002u
#define CYVAL_UDB_P_U_OUT1_FF0 0x00000003u
#define CYVAL_UDB_P_U_OUT1_CE1 0x00000004u
#define CYVAL_UDB_P_U_OUT1_CL1 0x00000005u
#define CYVAL_UDB_P_U_OUT1_Z1 0x00000006u
#define CYVAL_UDB_P_U_OUT1_FF1 0x00000007u
#define CYVAL_UDB_P_U_OUT1_OV_MSB 0x00000008u
#define CYVAL_UDB_P_U_OUT1_CO_MSB 0x00000009u
#define CYVAL_UDB_P_U_OUT1_CMSBO 0x0000000au
#define CYVAL_UDB_P_U_OUT1_SO 0x0000000bu
#define CYVAL_UDB_P_U_OUT1_F0_BLK_STAT 0x0000000cu
#define CYVAL_UDB_P_U_OUT1_F1_BLK_STAT 0x0000000du
#define CYVAL_UDB_P_U_OUT1_F0_BUS_STAT 0x0000000eu
#define CYVAL_UDB_P_U_OUT1_F1_BUS_STAT 0x0000000fu
#define CYREG_UDB_P0_U0_CFG6 0x400f3046u
#define CYFLD_UDB_P_U_OUT2__OFFSET 0x00000000u
#define CYFLD_UDB_P_U_OUT2__SIZE 0x00000004u
#define CYVAL_UDB_P_U_OUT2_CE0 0x00000000u
#define CYVAL_UDB_P_U_OUT2_CL0 0x00000001u
#define CYVAL_UDB_P_U_OUT2_Z0 0x00000002u
#define CYVAL_UDB_P_U_OUT2_FF0 0x00000003u
#define CYVAL_UDB_P_U_OUT2_CE1 0x00000004u
#define CYVAL_UDB_P_U_OUT2_CL1 0x00000005u
#define CYVAL_UDB_P_U_OUT2_Z1 0x00000006u
#define CYVAL_UDB_P_U_OUT2_FF1 0x00000007u
#define CYVAL_UDB_P_U_OUT2_OV_MSB 0x00000008u
#define CYVAL_UDB_P_U_OUT2_CO_MSB 0x00000009u
#define CYVAL_UDB_P_U_OUT2_CMSBO 0x0000000au
#define CYVAL_UDB_P_U_OUT2_SO 0x0000000bu
#define CYVAL_UDB_P_U_OUT2_F0_BLK_STAT 0x0000000cu
#define CYVAL_UDB_P_U_OUT2_F1_BLK_STAT 0x0000000du
#define CYVAL_UDB_P_U_OUT2_F0_BUS_STAT 0x0000000eu
#define CYVAL_UDB_P_U_OUT2_F1_BUS_STAT 0x0000000fu
#define CYFLD_UDB_P_U_OUT3__OFFSET 0x00000004u
#define CYFLD_UDB_P_U_OUT3__SIZE 0x00000004u
#define CYVAL_UDB_P_U_OUT3_CE0 0x00000000u
#define CYVAL_UDB_P_U_OUT3_CL0 0x00000001u
#define CYVAL_UDB_P_U_OUT3_Z0 0x00000002u
#define CYVAL_UDB_P_U_OUT3_FF0 0x00000003u
#define CYVAL_UDB_P_U_OUT3_CE1 0x00000004u
#define CYVAL_UDB_P_U_OUT3_CL1 0x00000005u
#define CYVAL_UDB_P_U_OUT3_Z1 0x00000006u
#define CYVAL_UDB_P_U_OUT3_FF1 0x00000007u
#define CYVAL_UDB_P_U_OUT3_OV_MSB 0x00000008u
#define CYVAL_UDB_P_U_OUT3_CO_MSB 0x00000009u
#define CYVAL_UDB_P_U_OUT3_CMSBO 0x0000000au
#define CYVAL_UDB_P_U_OUT3_SO 0x0000000bu
#define CYVAL_UDB_P_U_OUT3_F0_BLK_STAT 0x0000000cu
#define CYVAL_UDB_P_U_OUT3_F1_BLK_STAT 0x0000000du
#define CYVAL_UDB_P_U_OUT3_F0_BUS_STAT 0x0000000eu
#define CYVAL_UDB_P_U_OUT3_F1_BUS_STAT 0x0000000fu
#define CYREG_UDB_P0_U0_CFG7 0x400f3047u
#define CYFLD_UDB_P_U_OUT4__OFFSET 0x00000000u
#define CYFLD_UDB_P_U_OUT4__SIZE 0x00000004u
#define CYVAL_UDB_P_U_OUT4_CE0 0x00000000u
#define CYVAL_UDB_P_U_OUT4_CL0 0x00000001u
#define CYVAL_UDB_P_U_OUT4_Z0 0x00000002u
#define CYVAL_UDB_P_U_OUT4_FF0 0x00000003u
#define CYVAL_UDB_P_U_OUT4_CE1 0x00000004u
#define CYVAL_UDB_P_U_OUT4_CL1 0x00000005u
#define CYVAL_UDB_P_U_OUT4_Z1 0x00000006u
#define CYVAL_UDB_P_U_OUT4_FF1 0x00000007u
#define CYVAL_UDB_P_U_OUT4_OV_MSB 0x00000008u
#define CYVAL_UDB_P_U_OUT4_CO_MSB 0x00000009u
#define CYVAL_UDB_P_U_OUT4_CMSBO 0x0000000au
#define CYVAL_UDB_P_U_OUT4_SO 0x0000000bu
#define CYVAL_UDB_P_U_OUT4_F0_BLK_STAT 0x0000000cu
#define CYVAL_UDB_P_U_OUT4_F1_BLK_STAT 0x0000000du
#define CYVAL_UDB_P_U_OUT4_F0_BUS_STAT 0x0000000eu
#define CYVAL_UDB_P_U_OUT4_F1_BUS_STAT 0x0000000fu
#define CYFLD_UDB_P_U_OUT5__OFFSET 0x00000004u
#define CYFLD_UDB_P_U_OUT5__SIZE 0x00000004u
#define CYVAL_UDB_P_U_OUT5_CE0 0x00000000u
#define CYVAL_UDB_P_U_OUT5_CL0 0x00000001u
#define CYVAL_UDB_P_U_OUT5_Z0 0x00000002u
#define CYVAL_UDB_P_U_OUT5_FF0 0x00000003u
#define CYVAL_UDB_P_U_OUT5_CE1 0x00000004u
#define CYVAL_UDB_P_U_OUT5_CL1 0x00000005u
#define CYVAL_UDB_P_U_OUT5_Z1 0x00000006u
#define CYVAL_UDB_P_U_OUT5_FF1 0x00000007u
#define CYVAL_UDB_P_U_OUT5_OV_MSB 0x00000008u
#define CYVAL_UDB_P_U_OUT5_CO_MSB 0x00000009u
#define CYVAL_UDB_P_U_OUT5_CMSBO 0x0000000au
#define CYVAL_UDB_P_U_OUT5_SO 0x0000000bu
#define CYVAL_UDB_P_U_OUT5_F0_BLK_STAT 0x0000000cu
#define CYVAL_UDB_P_U_OUT5_F1_BLK_STAT 0x0000000du
#define CYVAL_UDB_P_U_OUT5_F0_BUS_STAT 0x0000000eu
#define CYVAL_UDB_P_U_OUT5_F1_BUS_STAT 0x0000000fu
#define CYREG_UDB_P0_U0_CFG8 0x400f3048u
#define CYFLD_UDB_P_U_OUT_SYNC__OFFSET 0x00000000u
#define CYFLD_UDB_P_U_OUT_SYNC__SIZE 0x00000006u
#define CYVAL_UDB_P_U_OUT_SYNC_REGISTERED 0x00000000u
#define CYVAL_UDB_P_U_OUT_SYNC_COMBINATIONAL 0x00000001u
#define CYFLD_UDB_P_U_NC6__OFFSET 0x00000006u
#define CYFLD_UDB_P_U_NC6__SIZE 0x00000001u
#define CYREG_UDB_P0_U0_CFG9 0x400f3049u
#define CYFLD_UDB_P_U_AMASK__OFFSET 0x00000000u
#define CYFLD_UDB_P_U_AMASK__SIZE 0x00000008u
#define CYREG_UDB_P0_U0_CFG10 0x400f304au
#define CYFLD_UDB_P_U_CMASK0__OFFSET 0x00000000u
#define CYFLD_UDB_P_U_CMASK0__SIZE 0x00000008u
#define CYREG_UDB_P0_U0_CFG11 0x400f304bu
#define CYREG_UDB_P0_U0_CFG12 0x400f304cu
#define CYFLD_UDB_P_U_SI_SELA__OFFSET 0x00000000u
#define CYFLD_UDB_P_U_SI_SELA__SIZE 0x00000002u
#define CYVAL_UDB_P_U_SI_SELA_DEFAULT 0x00000000u
#define CYVAL_UDB_P_U_SI_SELA_REGISTERED 0x00000001u
#define CYVAL_UDB_P_U_SI_SELA_ROUTE 0x00000002u
#define CYVAL_UDB_P_U_SI_SELA_CHAIN 0x00000003u
#define CYFLD_UDB_P_U_SI_SELB__OFFSET 0x00000002u
#define CYFLD_UDB_P_U_SI_SELB__SIZE 0x00000002u
#define CYVAL_UDB_P_U_SI_SELB_DEFAULT 0x00000000u
#define CYVAL_UDB_P_U_SI_SELB_REGISTERED 0x00000001u
#define CYVAL_UDB_P_U_SI_SELB_ROUTE 0x00000002u
#define CYVAL_UDB_P_U_SI_SELB_CHAIN 0x00000003u
#define CYFLD_UDB_P_U_DEF_SI__OFFSET 0x00000004u
#define CYFLD_UDB_P_U_DEF_SI__SIZE 0x00000001u
#define CYVAL_UDB_P_U_DEF_SI_DEFAULT_0 0x00000000u
#define CYVAL_UDB_P_U_DEF_SI_DEFAULT_1 0x00000001u
#define CYFLD_UDB_P_U_AMASK_EN__OFFSET 0x00000005u
#define CYFLD_UDB_P_U_AMASK_EN__SIZE 0x00000001u
#define CYVAL_UDB_P_U_AMASK_EN_DISABLE 0x00000000u
#define CYVAL_UDB_P_U_AMASK_EN_ENABLE 0x00000001u
#define CYFLD_UDB_P_U_CMASK0_EN__OFFSET 0x00000006u
#define CYFLD_UDB_P_U_CMASK0_EN__SIZE 0x00000001u
#define CYVAL_UDB_P_U_CMASK0_EN_DISABLE 0x00000000u
#define CYVAL_UDB_P_U_CMASK0_EN_ENABLE 0x00000001u
#define CYFLD_UDB_P_U_CMASK1_EN__OFFSET 0x00000007u
#define CYFLD_UDB_P_U_CMASK1_EN__SIZE 0x00000001u
#define CYVAL_UDB_P_U_CMASK1_EN_DISABLE 0x00000000u
#define CYVAL_UDB_P_U_CMASK1_EN_ENABLE 0x00000001u
#define CYREG_UDB_P0_U0_CFG13 0x400f304du
#define CYFLD_UDB_P_U_CI_SELA__OFFSET 0x00000000u
#define CYFLD_UDB_P_U_CI_SELA__SIZE 0x00000002u
#define CYVAL_UDB_P_U_CI_SELA_DEFAULT 0x00000000u
#define CYVAL_UDB_P_U_CI_SELA_REGISTERED 0x00000001u
#define CYVAL_UDB_P_U_CI_SELA_ROUTE 0x00000002u
#define CYVAL_UDB_P_U_CI_SELA_CHAIN 0x00000003u
#define CYFLD_UDB_P_U_CI_SELB__OFFSET 0x00000002u
#define CYFLD_UDB_P_U_CI_SELB__SIZE 0x00000002u
#define CYVAL_UDB_P_U_CI_SELB_DEFAULT 0x00000000u
#define CYVAL_UDB_P_U_CI_SELB_REGISTERED 0x00000001u
#define CYVAL_UDB_P_U_CI_SELB_ROUTE 0x00000002u
#define CYVAL_UDB_P_U_CI_SELB_CHAIN 0x00000003u
#define CYFLD_UDB_P_U_CMP_SELA__OFFSET 0x00000004u
#define CYFLD_UDB_P_U_CMP_SELA__SIZE 0x00000002u
#define CYVAL_UDB_P_U_CMP_SELA_A1_D1 0x00000000u
#define CYVAL_UDB_P_U_CMP_SELA_A1_A0 0x00000001u
#define CYVAL_UDB_P_U_CMP_SELA_A0_D1 0x00000002u
#define CYVAL_UDB_P_U_CMP_SELA_A0_A0 0x00000003u
#define CYFLD_UDB_P_U_CMP_SELB__OFFSET 0x00000006u
#define CYFLD_UDB_P_U_CMP_SELB__SIZE 0x00000002u
#define CYVAL_UDB_P_U_CMP_SELB_A1_D1 0x00000000u
#define CYVAL_UDB_P_U_CMP_SELB_A1_A0 0x00000001u
#define CYVAL_UDB_P_U_CMP_SELB_A0_D1 0x00000002u
#define CYVAL_UDB_P_U_CMP_SELB_A0_A0 0x00000003u
#define CYREG_UDB_P0_U0_CFG14 0x400f304eu
#define CYFLD_UDB_P_U_CHAIN0__OFFSET 0x00000000u
#define CYFLD_UDB_P_U_CHAIN0__SIZE 0x00000001u
#define CYVAL_UDB_P_U_CHAIN0_DISABLE 0x00000000u
#define CYVAL_UDB_P_U_CHAIN0_ENABLE 0x00000001u
#define CYFLD_UDB_P_U_CHAIN1__OFFSET 0x00000001u
#define CYFLD_UDB_P_U_CHAIN1__SIZE 0x00000001u
#define CYVAL_UDB_P_U_CHAIN1_DISABLE 0x00000000u
#define CYVAL_UDB_P_U_CHAIN1_ENABLE 0x00000001u
#define CYFLD_UDB_P_U_CHAIN_FB__OFFSET 0x00000002u
#define CYFLD_UDB_P_U_CHAIN_FB__SIZE 0x00000001u
#define CYVAL_UDB_P_U_CHAIN_FB_DISABLE 0x00000000u
#define CYVAL_UDB_P_U_CHAIN_FB_ENABLE 0x00000001u
#define CYFLD_UDB_P_U_CHAIN_CMSB__OFFSET 0x00000003u
#define CYFLD_UDB_P_U_CHAIN_CMSB__SIZE 0x00000001u
#define CYVAL_UDB_P_U_CHAIN_CMSB_DISABLE 0x00000000u
#define CYVAL_UDB_P_U_CHAIN_CMSB_ENABLE 0x00000001u
#define CYFLD_UDB_P_U_MSB_SEL__OFFSET 0x00000004u
#define CYFLD_UDB_P_U_MSB_SEL__SIZE 0x00000003u
#define CYVAL_UDB_P_U_MSB_SEL_BIT0 0x00000000u
#define CYVAL_UDB_P_U_MSB_SEL_BIT1 0x00000001u
#define CYVAL_UDB_P_U_MSB_SEL_BIT2 0x00000002u
#define CYVAL_UDB_P_U_MSB_SEL_BIT3 0x00000003u
#define CYVAL_UDB_P_U_MSB_SEL_BIT4 0x00000004u
#define CYVAL_UDB_P_U_MSB_SEL_BIT5 0x00000005u
#define CYVAL_UDB_P_U_MSB_SEL_BIT6 0x00000006u
#define CYVAL_UDB_P_U_MSB_SEL_BIT7 0x00000007u
#define CYFLD_UDB_P_U_MSB_EN__OFFSET 0x00000007u
#define CYFLD_UDB_P_U_MSB_EN__SIZE 0x00000001u
#define CYVAL_UDB_P_U_MSB_EN_DISABLE 0x00000000u
#define CYVAL_UDB_P_U_MSB_EN_ENABLE 0x00000001u
#define CYREG_UDB_P0_U0_CFG15 0x400f304fu
#define CYFLD_UDB_P_U_F0_INSEL__OFFSET 0x00000000u
#define CYFLD_UDB_P_U_F0_INSEL__SIZE 0x00000002u
#define CYVAL_UDB_P_U_F0_INSEL_INPUT 0x00000000u
#define CYVAL_UDB_P_U_F0_INSEL_OUTPUT_A0 0x00000001u
#define CYVAL_UDB_P_U_F0_INSEL_OUTPUT_A1 0x00000002u
#define CYVAL_UDB_P_U_F0_INSEL_OUTPUT_ALU 0x00000003u
#define CYFLD_UDB_P_U_F1_INSEL__OFFSET 0x00000002u
#define CYFLD_UDB_P_U_F1_INSEL__SIZE 0x00000002u
#define CYVAL_UDB_P_U_F1_INSEL_INPUT 0x00000000u
#define CYVAL_UDB_P_U_F1_INSEL_OUTPUT_A0 0x00000001u
#define CYVAL_UDB_P_U_F1_INSEL_OUTPUT_A1 0x00000002u
#define CYVAL_UDB_P_U_F1_INSEL_OUTPUT_ALU 0x00000003u
#define CYFLD_UDB_P_U_MSB_SI__OFFSET 0x00000004u
#define CYFLD_UDB_P_U_MSB_SI__SIZE 0x00000001u
#define CYVAL_UDB_P_U_MSB_SI_DEFAULT 0x00000000u
#define CYVAL_UDB_P_U_MSB_SI_MSB 0x00000001u
#define CYFLD_UDB_P_U_PI_DYN__OFFSET 0x00000005u
#define CYFLD_UDB_P_U_PI_DYN__SIZE 0x00000001u
#define CYVAL_UDB_P_U_PI_DYN_DISABLE 0x00000000u
#define CYVAL_UDB_P_U_PI_DYN_ENABLE 0x00000001u
#define CYFLD_UDB_P_U_SHIFT_SEL__OFFSET 0x00000006u
#define CYFLD_UDB_P_U_SHIFT_SEL__SIZE 0x00000001u
#define CYVAL_UDB_P_U_SHIFT_SEL_SOL_MSB 0x00000000u
#define CYVAL_UDB_P_U_SHIFT_SEL_SOR 0x00000001u
#define CYFLD_UDB_P_U_PI_SEL__OFFSET 0x00000007u
#define CYFLD_UDB_P_U_PI_SEL__SIZE 0x00000001u
#define CYVAL_UDB_P_U_PI_SEL_NORMAL 0x00000000u
#define CYVAL_UDB_P_U_PI_SEL_PARALLEL 0x00000001u
#define CYREG_UDB_P0_U0_CFG16 0x400f3050u
#define CYFLD_UDB_P_U_WRK16_CONCAT__OFFSET 0x00000000u
#define CYFLD_UDB_P_U_WRK16_CONCAT__SIZE 0x00000001u
#define CYVAL_UDB_P_U_WRK16_CONCAT_DEFAULT 0x00000000u
#define CYVAL_UDB_P_U_WRK16_CONCAT_CONCATENATE 0x00000001u
#define CYFLD_UDB_P_U_EXT_CRCPRS__OFFSET 0x00000001u
#define CYFLD_UDB_P_U_EXT_CRCPRS__SIZE 0x00000001u
#define CYVAL_UDB_P_U_EXT_CRCPRS_INTERNAL 0x00000000u
#define CYVAL_UDB_P_U_EXT_CRCPRS_EXTERNAL 0x00000001u
#define CYFLD_UDB_P_U_FIFO_ASYNC__OFFSET 0x00000002u
#define CYFLD_UDB_P_U_FIFO_ASYNC__SIZE 0x00000001u
#define CYVAL_UDB_P_U_FIFO_ASYNC_DISABLE 0x00000000u
#define CYVAL_UDB_P_U_FIFO_ASYNC_ENABLE 0x00000001u
#define CYFLD_UDB_P_U_FIFO_EDGE__OFFSET 0x00000003u
#define CYFLD_UDB_P_U_FIFO_EDGE__SIZE 0x00000001u
#define CYVAL_UDB_P_U_FIFO_EDGE_LEVEL 0x00000000u
#define CYVAL_UDB_P_U_FIFO_EDGE_EDGE 0x00000001u
#define CYFLD_UDB_P_U_FIFO_CAP__OFFSET 0x00000004u
#define CYFLD_UDB_P_U_FIFO_CAP__SIZE 0x00000001u
#define CYVAL_UDB_P_U_FIFO_CAP_DISABLE 0x00000000u
#define CYVAL_UDB_P_U_FIFO_CAP_ENABLE 0x00000001u
#define CYFLD_UDB_P_U_FIFO_FAST__OFFSET 0x00000005u
#define CYFLD_UDB_P_U_FIFO_FAST__SIZE 0x00000001u
#define CYVAL_UDB_P_U_FIFO_FAST_DISABLE 0x00000000u
#define CYVAL_UDB_P_U_FIFO_FAST_ENABLE 0x00000001u
#define CYFLD_UDB_P_U_F0_CK_INV__OFFSET 0x00000006u
#define CYFLD_UDB_P_U_F0_CK_INV__SIZE 0x00000001u
#define CYVAL_UDB_P_U_F0_CK_INV_NORMAL 0x00000000u
#define CYVAL_UDB_P_U_F0_CK_INV_INVERT 0x00000001u
#define CYFLD_UDB_P_U_F1_CK_INV__OFFSET 0x00000007u
#define CYFLD_UDB_P_U_F1_CK_INV__SIZE 0x00000001u
#define CYVAL_UDB_P_U_F1_CK_INV_NORMAL 0x00000000u
#define CYVAL_UDB_P_U_F1_CK_INV_INVERT 0x00000001u
#define CYREG_UDB_P0_U0_CFG17 0x400f3051u
#define CYFLD_UDB_P_U_F0_DYN__OFFSET 0x00000000u
#define CYFLD_UDB_P_U_F0_DYN__SIZE 0x00000001u
#define CYVAL_UDB_P_U_F0_DYN_STATIC 0x00000000u
#define CYVAL_UDB_P_U_F0_DYN_DYNAMIC 0x00000001u
#define CYFLD_UDB_P_U_F1_DYN__OFFSET 0x00000001u
#define CYFLD_UDB_P_U_F1_DYN__SIZE 0x00000001u
#define CYVAL_UDB_P_U_F1_DYN_STATIC 0x00000000u
#define CYVAL_UDB_P_U_F1_DYN_DYNAMIC 0x00000001u
#define CYFLD_UDB_P_U_NC2__OFFSET 0x00000002u
#define CYFLD_UDB_P_U_NC2__SIZE 0x00000001u
#define CYFLD_UDB_P_U_FIFO_ADD_SYNC__OFFSET 0x00000004u
#define CYFLD_UDB_P_U_FIFO_ADD_SYNC__SIZE 0x00000001u
#define CYVAL_UDB_P_U_FIFO_ADD_SYNC_DISABLE 0x00000000u
#define CYVAL_UDB_P_U_FIFO_ADD_SYNC_ENABLE 0x00000001u
#define CYREG_UDB_P0_U0_CFG18 0x400f3052u
#define CYFLD_UDB_P_U_CTL_MD0__OFFSET 0x00000000u
#define CYFLD_UDB_P_U_CTL_MD0__SIZE 0x00000008u
#define CYVAL_UDB_P_U_CTL_MD0_DIRECT 0x00000000u
#define CYVAL_UDB_P_U_CTL_MD0_SYNC 0x00000001u
#define CYVAL_UDB_P_U_CTL_MD0_DOUBLE_SYNC 0x00000002u
#define CYVAL_UDB_P_U_CTL_MD0_PULSE 0x00000003u
#define CYREG_UDB_P0_U0_CFG19 0x400f3053u
#define CYFLD_UDB_P_U_CTL_MD1__OFFSET 0x00000000u
#define CYFLD_UDB_P_U_CTL_MD1__SIZE 0x00000008u
#define CYVAL_UDB_P_U_CTL_MD1_DIRECT 0x00000000u
#define CYVAL_UDB_P_U_CTL_MD1_SYNC 0x00000001u
#define CYVAL_UDB_P_U_CTL_MD1_DOUBLE_SYNC 0x00000002u
#define CYVAL_UDB_P_U_CTL_MD1_PULSE 0x00000003u
#define CYREG_UDB_P0_U0_CFG20 0x400f3054u
#define CYFLD_UDB_P_U_STAT_MD__OFFSET 0x00000000u
#define CYFLD_UDB_P_U_STAT_MD__SIZE 0x00000008u
#define CYREG_UDB_P0_U0_CFG21 0x400f3055u
#define CYFLD_UDB_P_U_NC0__OFFSET 0x00000000u
#define CYFLD_UDB_P_U_NC0__SIZE 0x00000001u
#define CYREG_UDB_P0_U0_CFG22 0x400f3056u
#define CYFLD_UDB_P_U_SC_OUT_CTL__OFFSET 0x00000000u
#define CYFLD_UDB_P_U_SC_OUT_CTL__SIZE 0x00000002u
#define CYVAL_UDB_P_U_SC_OUT_CTL_CONTROL 0x00000000u
#define CYVAL_UDB_P_U_SC_OUT_CTL_PARALLEL 0x00000001u
#define CYVAL_UDB_P_U_SC_OUT_CTL_COUNTER 0x00000002u
#define CYVAL_UDB_P_U_SC_OUT_CTL_RESERVED 0x00000003u
#define CYFLD_UDB_P_U_SC_INT_MD__OFFSET 0x00000002u
#define CYFLD_UDB_P_U_SC_INT_MD__SIZE 0x00000001u
#define CYVAL_UDB_P_U_SC_INT_MD_NORMAL 0x00000000u
#define CYVAL_UDB_P_U_SC_INT_MD_INT_MODE 0x00000001u
#define CYFLD_UDB_P_U_SC_SYNC_MD__OFFSET 0x00000003u
#define CYFLD_UDB_P_U_SC_SYNC_MD__SIZE 0x00000001u
#define CYVAL_UDB_P_U_SC_SYNC_MD_NORMAL 0x00000000u
#define CYVAL_UDB_P_U_SC_SYNC_MD_SYNC_MODE 0x00000001u
#define CYFLD_UDB_P_U_SC_EXT_RES__OFFSET 0x00000004u
#define CYFLD_UDB_P_U_SC_EXT_RES__SIZE 0x00000001u
#define CYVAL_UDB_P_U_SC_EXT_RES_DISABLED 0x00000000u
#define CYVAL_UDB_P_U_SC_EXT_RES_ENABLED 0x00000001u
#define CYREG_UDB_P0_U0_CFG23 0x400f3057u
#define CYFLD_UDB_P_U_CNT_LD_SEL__OFFSET 0x00000000u
#define CYFLD_UDB_P_U_CNT_LD_SEL__SIZE 0x00000002u
#define CYVAL_UDB_P_U_CNT_LD_SEL_SC_IN0 0x00000000u
#define CYVAL_UDB_P_U_CNT_LD_SEL_SC_IN1 0x00000001u
#define CYVAL_UDB_P_U_CNT_LD_SEL_SC_IN2 0x00000002u
#define CYVAL_UDB_P_U_CNT_LD_SEL_SC_IN3 0x00000003u
#define CYFLD_UDB_P_U_CNT_EN_SEL__OFFSET 0x00000002u
#define CYFLD_UDB_P_U_CNT_EN_SEL__SIZE 0x00000002u
#define CYVAL_UDB_P_U_CNT_EN_SEL_SC_IN4 0x00000000u
#define CYVAL_UDB_P_U_CNT_EN_SEL_SC_IN5 0x00000001u
#define CYVAL_UDB_P_U_CNT_EN_SEL_SC_IN6 0x00000002u
#define CYVAL_UDB_P_U_CNT_EN_SEL_SC_IO 0x00000003u
#define CYFLD_UDB_P_U_ROUTE_LD__OFFSET 0x00000004u
#define CYFLD_UDB_P_U_ROUTE_LD__SIZE 0x00000001u
#define CYVAL_UDB_P_U_ROUTE_LD_DISABLE 0x00000000u
#define CYVAL_UDB_P_U_ROUTE_LD_ROUTED 0x00000001u
#define CYFLD_UDB_P_U_ROUTE_EN__OFFSET 0x00000005u
#define CYFLD_UDB_P_U_ROUTE_EN__SIZE 0x00000001u
#define CYVAL_UDB_P_U_ROUTE_EN_DISABLE 0x00000000u
#define CYVAL_UDB_P_U_ROUTE_EN_ROUTED 0x00000001u
#define CYFLD_UDB_P_U_ALT_CNT__OFFSET 0x00000006u
#define CYFLD_UDB_P_U_ALT_CNT__SIZE 0x00000001u
#define CYVAL_UDB_P_U_ALT_CNT_DEFAULT_MODE 0x00000000u
#define CYVAL_UDB_P_U_ALT_CNT_ALT_MODE 0x00000001u
#define CYREG_UDB_P0_U0_CFG24 0x400f3058u
#define CYFLD_UDB_P_U_RC_EN_SEL__OFFSET 0x00000000u
#define CYFLD_UDB_P_U_RC_EN_SEL__SIZE 0x00000002u
#define CYVAL_UDB_P_U_RC_EN_SEL_RC_IN0 0x00000000u
#define CYVAL_UDB_P_U_RC_EN_SEL_RC_IN1 0x00000001u
#define CYVAL_UDB_P_U_RC_EN_SEL_RC_IN2 0x00000002u
#define CYVAL_UDB_P_U_RC_EN_SEL_RC_IN3 0x00000003u
#define CYFLD_UDB_P_U_RC_EN_MODE__OFFSET 0x00000002u
#define CYFLD_UDB_P_U_RC_EN_MODE__SIZE 0x00000002u
#define CYVAL_UDB_P_U_RC_EN_MODE_OFF 0x00000000u
#define CYVAL_UDB_P_U_RC_EN_MODE_ON 0x00000001u
#define CYVAL_UDB_P_U_RC_EN_MODE_POSEDGE 0x00000002u
#define CYVAL_UDB_P_U_RC_EN_MODE_LEVEL 0x00000003u
#define CYFLD_UDB_P_U_RC_EN_INV__OFFSET 0x00000004u
#define CYFLD_UDB_P_U_RC_EN_INV__SIZE 0x00000001u
#define CYVAL_UDB_P_U_RC_EN_INV_NOINV 0x00000000u
#define CYVAL_UDB_P_U_RC_EN_INV_INVERT 0x00000001u
#define CYFLD_UDB_P_U_RC_INV__OFFSET 0x00000005u
#define CYFLD_UDB_P_U_RC_INV__SIZE 0x00000001u
#define CYVAL_UDB_P_U_RC_INV_NOINV 0x00000000u
#define CYVAL_UDB_P_U_RC_INV_INVERT 0x00000001u
#define CYFLD_UDB_P_U_RC_RES_SEL0_OR_FRES__OFFSET 0x00000006u
#define CYFLD_UDB_P_U_RC_RES_SEL0_OR_FRES__SIZE 0x00000001u
#define CYFLD_UDB_P_U_RC_RES_SEL1__OFFSET 0x00000007u
#define CYFLD_UDB_P_U_RC_RES_SEL1__SIZE 0x00000001u
#define CYREG_UDB_P0_U0_CFG25 0x400f3059u
#define CYREG_UDB_P0_U0_CFG26 0x400f305au
#define CYREG_UDB_P0_U0_CFG27 0x400f305bu
#define CYREG_UDB_P0_U0_CFG28 0x400f305cu
#define CYFLD_UDB_P_U_PLD0_CK_SEL__OFFSET 0x00000000u
#define CYFLD_UDB_P_U_PLD0_CK_SEL__SIZE 0x00000004u
#define CYVAL_UDB_P_U_PLD0_CK_SEL_GCLK0 0x00000000u
#define CYVAL_UDB_P_U_PLD0_CK_SEL_GCLK1 0x00000001u
#define CYVAL_UDB_P_U_PLD0_CK_SEL_GCLK2 0x00000002u
#define CYVAL_UDB_P_U_PLD0_CK_SEL_GCLK3 0x00000003u
#define CYVAL_UDB_P_U_PLD0_CK_SEL_GCLK4 0x00000004u
#define CYVAL_UDB_P_U_PLD0_CK_SEL_GCLK5 0x00000005u
#define CYVAL_UDB_P_U_PLD0_CK_SEL_GCLK6 0x00000006u
#define CYVAL_UDB_P_U_PLD0_CK_SEL_GCLK7 0x00000007u
#define CYVAL_UDB_P_U_PLD0_CK_SEL_EXT_CLK 0x00000008u
#define CYVAL_UDB_P_U_PLD0_CK_SEL_SYSCLK 0x00000009u
#define CYFLD_UDB_P_U_PLD1_CK_SEL__OFFSET 0x00000004u
#define CYFLD_UDB_P_U_PLD1_CK_SEL__SIZE 0x00000004u
#define CYVAL_UDB_P_U_PLD1_CK_SEL_GCLK0 0x00000000u
#define CYVAL_UDB_P_U_PLD1_CK_SEL_GCLK1 0x00000001u
#define CYVAL_UDB_P_U_PLD1_CK_SEL_GCLK2 0x00000002u
#define CYVAL_UDB_P_U_PLD1_CK_SEL_GCLK3 0x00000003u
#define CYVAL_UDB_P_U_PLD1_CK_SEL_GCLK4 0x00000004u
#define CYVAL_UDB_P_U_PLD1_CK_SEL_GCLK5 0x00000005u
#define CYVAL_UDB_P_U_PLD1_CK_SEL_GCLK6 0x00000006u
#define CYVAL_UDB_P_U_PLD1_CK_SEL_GCLK7 0x00000007u
#define CYVAL_UDB_P_U_PLD1_CK_SEL_EXT_CLK 0x00000008u
#define CYVAL_UDB_P_U_PLD1_CK_SEL_SYSCLK 0x00000009u
#define CYREG_UDB_P0_U0_CFG29 0x400f305du
#define CYFLD_UDB_P_U_DP_CK_SEL__OFFSET 0x00000000u
#define CYFLD_UDB_P_U_DP_CK_SEL__SIZE 0x00000004u
#define CYVAL_UDB_P_U_DP_CK_SEL_GCLK0 0x00000000u
#define CYVAL_UDB_P_U_DP_CK_SEL_GCLK1 0x00000001u
#define CYVAL_UDB_P_U_DP_CK_SEL_GCLK2 0x00000002u
#define CYVAL_UDB_P_U_DP_CK_SEL_GCLK3 0x00000003u
#define CYVAL_UDB_P_U_DP_CK_SEL_GCLK4 0x00000004u
#define CYVAL_UDB_P_U_DP_CK_SEL_GCLK5 0x00000005u
#define CYVAL_UDB_P_U_DP_CK_SEL_GCLK6 0x00000006u
#define CYVAL_UDB_P_U_DP_CK_SEL_GCLK7 0x00000007u
#define CYVAL_UDB_P_U_DP_CK_SEL_EXT_CLK 0x00000008u
#define CYVAL_UDB_P_U_DP_CK_SEL_SYSCLK 0x00000009u
#define CYFLD_UDB_P_U_SC_CK_SEL__OFFSET 0x00000004u
#define CYFLD_UDB_P_U_SC_CK_SEL__SIZE 0x00000004u
#define CYVAL_UDB_P_U_SC_CK_SEL_GCLK0 0x00000000u
#define CYVAL_UDB_P_U_SC_CK_SEL_GCLK1 0x00000001u
#define CYVAL_UDB_P_U_SC_CK_SEL_GCLK2 0x00000002u
#define CYVAL_UDB_P_U_SC_CK_SEL_GCLK3 0x00000003u
#define CYVAL_UDB_P_U_SC_CK_SEL_GCLK4 0x00000004u
#define CYVAL_UDB_P_U_SC_CK_SEL_GCLK5 0x00000005u
#define CYVAL_UDB_P_U_SC_CK_SEL_GCLK6 0x00000006u
#define CYVAL_UDB_P_U_SC_CK_SEL_GCLK7 0x00000007u
#define CYVAL_UDB_P_U_SC_CK_SEL_EXT_CLK 0x00000008u
#define CYVAL_UDB_P_U_SC_CK_SEL_SYSCLK 0x00000009u
#define CYREG_UDB_P0_U0_CFG30 0x400f305eu
#define CYFLD_UDB_P_U_RES_SEL__OFFSET 0x00000000u
#define CYFLD_UDB_P_U_RES_SEL__SIZE 0x00000002u
#define CYVAL_UDB_P_U_RES_SEL_RC_IN0 0x00000000u
#define CYVAL_UDB_P_U_RES_SEL_RC_IN1 0x00000001u
#define CYVAL_UDB_P_U_RES_SEL_RC_IN2 0x00000002u
#define CYVAL_UDB_P_U_RES_SEL_RC_IN3 0x00000003u
#define CYFLD_UDB_P_U_RES_POL__OFFSET 0x00000002u
#define CYFLD_UDB_P_U_RES_POL__SIZE 0x00000001u
#define CYVAL_UDB_P_U_RES_POL_NEGATED 0x00000000u
#define CYVAL_UDB_P_U_RES_POL_ASSERTED 0x00000001u
#define CYFLD_UDB_P_U_EN_RES_CNTCTL__OFFSET 0x00000003u
#define CYFLD_UDB_P_U_EN_RES_CNTCTL__SIZE 0x00000001u
#define CYVAL_UDB_P_U_EN_RES_CNTCTL_DISABLE 0x00000000u
#define CYVAL_UDB_P_U_EN_RES_CNTCTL_ENABLE 0x00000001u
#define CYFLD_UDB_P_U_GUDB_WR__OFFSET 0x00000004u
#define CYFLD_UDB_P_U_GUDB_WR__SIZE 0x00000001u
#define CYVAL_UDB_P_U_GUDB_WR_DISABLE 0x00000000u
#define CYVAL_UDB_P_U_GUDB_WR_ENABLE 0x00000001u
#define CYFLD_UDB_P_U_DP_RES_POL__OFFSET 0x00000006u
#define CYFLD_UDB_P_U_DP_RES_POL__SIZE 0x00000001u
#define CYVAL_UDB_P_U_DP_RES_POL_NOINV 0x00000000u
#define CYVAL_UDB_P_U_DP_RES_POL_INVERT 0x00000001u
#define CYFLD_UDB_P_U_SC_RES_POL__OFFSET 0x00000007u
#define CYFLD_UDB_P_U_SC_RES_POL__SIZE 0x00000001u
#define CYVAL_UDB_P_U_SC_RES_POL_NOINV 0x00000000u
#define CYVAL_UDB_P_U_SC_RES_POL_INVERT 0x00000001u
#define CYREG_UDB_P0_U0_CFG31 0x400f305fu
#define CYFLD_UDB_P_U_ALT_RES__OFFSET 0x00000000u
#define CYFLD_UDB_P_U_ALT_RES__SIZE 0x00000001u
#define CYVAL_UDB_P_U_ALT_RES_COMPATIBLE 0x00000000u
#define CYVAL_UDB_P_U_ALT_RES_ALTERNATE 0x00000001u
#define CYFLD_UDB_P_U_EXT_SYNC__OFFSET 0x00000001u
#define CYFLD_UDB_P_U_EXT_SYNC__SIZE 0x00000001u
#define CYVAL_UDB_P_U_EXT_SYNC_DISABLE 0x00000000u
#define CYVAL_UDB_P_U_EXT_SYNC_ENABLE 0x00000001u
#define CYFLD_UDB_P_U_EN_RES_STAT__OFFSET 0x00000002u
#define CYFLD_UDB_P_U_EN_RES_STAT__SIZE 0x00000001u
#define CYVAL_UDB_P_U_EN_RES_STAT_NEGATED 0x00000000u
#define CYVAL_UDB_P_U_EN_RES_STAT_ASSERTED 0x00000001u
#define CYFLD_UDB_P_U_EN_RES_DP__OFFSET 0x00000003u
#define CYFLD_UDB_P_U_EN_RES_DP__SIZE 0x00000001u
#define CYVAL_UDB_P_U_EN_RES_DP_DISABLE 0x00000000u
#define CYVAL_UDB_P_U_EN_RES_DP_ENABLE 0x00000001u
#define CYFLD_UDB_P_U_EXT_CK_SEL__OFFSET 0x00000004u
#define CYFLD_UDB_P_U_EXT_CK_SEL__SIZE 0x00000002u
#define CYVAL_UDB_P_U_EXT_CK_SEL_RC_IN0 0x00000000u
#define CYVAL_UDB_P_U_EXT_CK_SEL_RC_IN1 0x00000001u
#define CYVAL_UDB_P_U_EXT_CK_SEL_RC_IN2 0x00000002u
#define CYVAL_UDB_P_U_EXT_CK_SEL_RC_IN3 0x00000003u
#define CYFLD_UDB_P_U_PLD0_RES_POL__OFFSET 0x00000006u
#define CYFLD_UDB_P_U_PLD0_RES_POL__SIZE 0x00000001u
#define CYVAL_UDB_P_U_PLD0_RES_POL_NOINV 0x00000000u
#define CYVAL_UDB_P_U_PLD0_RES_POL_INVERT 0x00000001u
#define CYFLD_UDB_P_U_PLD1_RES_POL__OFFSET 0x00000007u
#define CYFLD_UDB_P_U_PLD1_RES_POL__SIZE 0x00000001u
#define CYVAL_UDB_P_U_PLD1_RES_POL_NOINV 0x00000000u
#define CYVAL_UDB_P_U_PLD1_RES_POL_INVERT 0x00000001u
#define CYREG_UDB_P0_U0_DCFG0 0x400f3060u
#define CYFLD_UDB_P_U_CMP_SEL__OFFSET 0x00000000u
#define CYFLD_UDB_P_U_CMP_SEL__SIZE 0x00000001u
#define CYVAL_UDB_P_U_CMP_SEL_CFG_A 0x00000000u
#define CYVAL_UDB_P_U_CMP_SEL_CFG_B 0x00000001u
#define CYFLD_UDB_P_U_SI_SEL__OFFSET 0x00000001u
#define CYFLD_UDB_P_U_SI_SEL__SIZE 0x00000001u
#define CYVAL_UDB_P_U_SI_SEL_CFG_A 0x00000000u
#define CYVAL_UDB_P_U_SI_SEL_CFG_B 0x00000001u
#define CYFLD_UDB_P_U_CI_SEL__OFFSET 0x00000002u
#define CYFLD_UDB_P_U_CI_SEL__SIZE 0x00000001u
#define CYVAL_UDB_P_U_CI_SEL_CFG_A 0x00000000u
#define CYVAL_UDB_P_U_CI_SEL_CFG_B 0x00000001u
#define CYFLD_UDB_P_U_CFB_EN__OFFSET 0x00000003u
#define CYFLD_UDB_P_U_CFB_EN__SIZE 0x00000001u
#define CYVAL_UDB_P_U_CFB_EN_DISABLE 0x00000000u
#define CYVAL_UDB_P_U_CFB_EN_ENABLE 0x00000001u
#define CYFLD_UDB_P_U_A1_WR_SRC__OFFSET 0x00000004u
#define CYFLD_UDB_P_U_A1_WR_SRC__SIZE 0x00000002u
#define CYVAL_UDB_P_U_A1_WR_SRC_NOWRITE 0x00000000u
#define CYVAL_UDB_P_U_A1_WR_SRC_ALU 0x00000001u
#define CYVAL_UDB_P_U_A1_WR_SRC_D1 0x00000002u
#define CYVAL_UDB_P_U_A1_WR_SRC_F1 0x00000003u
#define CYFLD_UDB_P_U_A0_WR_SRC__OFFSET 0x00000006u
#define CYFLD_UDB_P_U_A0_WR_SRC__SIZE 0x00000002u
#define CYVAL_UDB_P_U_A0_WR_SRC_NOWRITE 0x00000000u
#define CYVAL_UDB_P_U_A0_WR_SRC_ALU 0x00000001u
#define CYVAL_UDB_P_U_A0_WR_SRC_D0 0x00000002u
#define CYVAL_UDB_P_U_A0_WR_SRC_F0 0x00000003u
#define CYFLD_UDB_P_U_SHIFT__OFFSET 0x00000008u
#define CYFLD_UDB_P_U_SHIFT__SIZE 0x00000002u
#define CYVAL_UDB_P_U_SHIFT_NOSHIFT 0x00000000u
#define CYVAL_UDB_P_U_SHIFT_LEFT 0x00000001u
#define CYVAL_UDB_P_U_SHIFT_RIGHT 0x00000002u
#define CYVAL_UDB_P_U_SHIFT_SWAP 0x00000003u
#define CYFLD_UDB_P_U_SRC_B__OFFSET 0x0000000au
#define CYFLD_UDB_P_U_SRC_B__SIZE 0x00000002u
#define CYVAL_UDB_P_U_SRC_B_D0 0x00000000u
#define CYVAL_UDB_P_U_SRC_B_D1 0x00000001u
#define CYVAL_UDB_P_U_SRC_B_A0 0x00000002u
#define CYVAL_UDB_P_U_SRC_B_A1 0x00000003u
#define CYFLD_UDB_P_U_SRC_A__OFFSET 0x0000000cu
#define CYFLD_UDB_P_U_SRC_A__SIZE 0x00000001u
#define CYVAL_UDB_P_U_SRC_A_A0 0x00000000u
#define CYVAL_UDB_P_U_SRC_A_A1 0x00000001u
#define CYFLD_UDB_P_U_FUNC__OFFSET 0x0000000du
#define CYFLD_UDB_P_U_FUNC__SIZE 0x00000003u
#define CYVAL_UDB_P_U_FUNC_PASS 0x00000000u
#define CYVAL_UDB_P_U_FUNC_INC_A 0x00000001u
#define CYVAL_UDB_P_U_FUNC_DEC_A 0x00000002u
#define CYVAL_UDB_P_U_FUNC_ADD 0x00000003u
#define CYVAL_UDB_P_U_FUNC_SUB 0x00000004u
#define CYVAL_UDB_P_U_FUNC_XOR 0x00000005u
#define CYVAL_UDB_P_U_FUNC_AND 0x00000006u
#define CYVAL_UDB_P_U_FUNC_OR 0x00000007u
#define CYREG_UDB_P0_U0_DCFG1 0x400f3062u
#define CYREG_UDB_P0_U0_DCFG2 0x400f3064u
#define CYREG_UDB_P0_U0_DCFG3 0x400f3066u
#define CYREG_UDB_P0_U0_DCFG4 0x400f3068u
#define CYREG_UDB_P0_U0_DCFG5 0x400f306au
#define CYREG_UDB_P0_U0_DCFG6 0x400f306cu
#define CYREG_UDB_P0_U0_DCFG7 0x400f306eu
#define CYDEV_UDB_P0_U1_BASE 0x400f3080u
#define CYDEV_UDB_P0_U1_SIZE 0x00000080u
#define CYREG_UDB_P0_U1_PLD_IT0 0x400f3080u
#define CYREG_UDB_P0_U1_PLD_IT1 0x400f3084u
#define CYREG_UDB_P0_U1_PLD_IT2 0x400f3088u
#define CYREG_UDB_P0_U1_PLD_IT3 0x400f308cu
#define CYREG_UDB_P0_U1_PLD_IT4 0x400f3090u
#define CYREG_UDB_P0_U1_PLD_IT5 0x400f3094u
#define CYREG_UDB_P0_U1_PLD_IT6 0x400f3098u
#define CYREG_UDB_P0_U1_PLD_IT7 0x400f309cu
#define CYREG_UDB_P0_U1_PLD_IT8 0x400f30a0u
#define CYREG_UDB_P0_U1_PLD_IT9 0x400f30a4u
#define CYREG_UDB_P0_U1_PLD_IT10 0x400f30a8u
#define CYREG_UDB_P0_U1_PLD_IT11 0x400f30acu
#define CYREG_UDB_P0_U1_PLD_ORT0 0x400f30b0u
#define CYREG_UDB_P0_U1_PLD_ORT1 0x400f30b2u
#define CYREG_UDB_P0_U1_PLD_ORT2 0x400f30b4u
#define CYREG_UDB_P0_U1_PLD_ORT3 0x400f30b6u
#define CYREG_UDB_P0_U1_PLD_MC_CFG_CEN_CONST 0x400f30b8u
#define CYREG_UDB_P0_U1_PLD_MC_CFG_XORFB 0x400f30bau
#define CYREG_UDB_P0_U1_PLD_MC_SET_RESET 0x400f30bcu
#define CYREG_UDB_P0_U1_PLD_MC_CFG_BYPASS 0x400f30beu
#define CYREG_UDB_P0_U1_CFG0 0x400f30c0u
#define CYREG_UDB_P0_U1_CFG1 0x400f30c1u
#define CYREG_UDB_P0_U1_CFG2 0x400f30c2u
#define CYREG_UDB_P0_U1_CFG3 0x400f30c3u
#define CYREG_UDB_P0_U1_CFG4 0x400f30c4u
#define CYREG_UDB_P0_U1_CFG5 0x400f30c5u
#define CYREG_UDB_P0_U1_CFG6 0x400f30c6u
#define CYREG_UDB_P0_U1_CFG7 0x400f30c7u
#define CYREG_UDB_P0_U1_CFG8 0x400f30c8u
#define CYREG_UDB_P0_U1_CFG9 0x400f30c9u
#define CYREG_UDB_P0_U1_CFG10 0x400f30cau
#define CYREG_UDB_P0_U1_CFG11 0x400f30cbu
#define CYREG_UDB_P0_U1_CFG12 0x400f30ccu
#define CYREG_UDB_P0_U1_CFG13 0x400f30cdu
#define CYREG_UDB_P0_U1_CFG14 0x400f30ceu
#define CYREG_UDB_P0_U1_CFG15 0x400f30cfu
#define CYREG_UDB_P0_U1_CFG16 0x400f30d0u
#define CYREG_UDB_P0_U1_CFG17 0x400f30d1u
#define CYREG_UDB_P0_U1_CFG18 0x400f30d2u
#define CYREG_UDB_P0_U1_CFG19 0x400f30d3u
#define CYREG_UDB_P0_U1_CFG20 0x400f30d4u
#define CYREG_UDB_P0_U1_CFG21 0x400f30d5u
#define CYREG_UDB_P0_U1_CFG22 0x400f30d6u
#define CYREG_UDB_P0_U1_CFG23 0x400f30d7u
#define CYREG_UDB_P0_U1_CFG24 0x400f30d8u
#define CYREG_UDB_P0_U1_CFG25 0x400f30d9u
#define CYREG_UDB_P0_U1_CFG26 0x400f30dau
#define CYREG_UDB_P0_U1_CFG27 0x400f30dbu
#define CYREG_UDB_P0_U1_CFG28 0x400f30dcu
#define CYREG_UDB_P0_U1_CFG29 0x400f30ddu
#define CYREG_UDB_P0_U1_CFG30 0x400f30deu
#define CYREG_UDB_P0_U1_CFG31 0x400f30dfu
#define CYREG_UDB_P0_U1_DCFG0 0x400f30e0u
#define CYREG_UDB_P0_U1_DCFG1 0x400f30e2u
#define CYREG_UDB_P0_U1_DCFG2 0x400f30e4u
#define CYREG_UDB_P0_U1_DCFG3 0x400f30e6u
#define CYREG_UDB_P0_U1_DCFG4 0x400f30e8u
#define CYREG_UDB_P0_U1_DCFG5 0x400f30eau
#define CYREG_UDB_P0_U1_DCFG6 0x400f30ecu
#define CYREG_UDB_P0_U1_DCFG7 0x400f30eeu
#define CYDEV_UDB_P0_ROUTE_BASE 0x400f3100u
#define CYDEV_UDB_P0_ROUTE_SIZE 0x00000100u
#define CYREG_UDB_P0_ROUTE_HC0 0x400f3100u
#define CYFLD_UDB_P_ROUTE_HC_BYTE__OFFSET 0x00000000u
#define CYFLD_UDB_P_ROUTE_HC_BYTE__SIZE 0x00000008u
#define CYREG_UDB_P0_ROUTE_HC1 0x400f3101u
#define CYREG_UDB_P0_ROUTE_HC2 0x400f3102u
#define CYREG_UDB_P0_ROUTE_HC3 0x400f3103u
#define CYREG_UDB_P0_ROUTE_HC4 0x400f3104u
#define CYREG_UDB_P0_ROUTE_HC5 0x400f3105u
#define CYREG_UDB_P0_ROUTE_HC6 0x400f3106u
#define CYREG_UDB_P0_ROUTE_HC7 0x400f3107u
#define CYREG_UDB_P0_ROUTE_HC8 0x400f3108u
#define CYREG_UDB_P0_ROUTE_HC9 0x400f3109u
#define CYREG_UDB_P0_ROUTE_HC10 0x400f310au
#define CYREG_UDB_P0_ROUTE_HC11 0x400f310bu
#define CYREG_UDB_P0_ROUTE_HC12 0x400f310cu
#define CYREG_UDB_P0_ROUTE_HC13 0x400f310du
#define CYREG_UDB_P0_ROUTE_HC14 0x400f310eu
#define CYREG_UDB_P0_ROUTE_HC15 0x400f310fu
#define CYREG_UDB_P0_ROUTE_HC16 0x400f3110u
#define CYREG_UDB_P0_ROUTE_HC17 0x400f3111u
#define CYREG_UDB_P0_ROUTE_HC18 0x400f3112u
#define CYREG_UDB_P0_ROUTE_HC19 0x400f3113u
#define CYREG_UDB_P0_ROUTE_HC20 0x400f3114u
#define CYREG_UDB_P0_ROUTE_HC21 0x400f3115u
#define CYREG_UDB_P0_ROUTE_HC22 0x400f3116u
#define CYREG_UDB_P0_ROUTE_HC23 0x400f3117u
#define CYREG_UDB_P0_ROUTE_HC24 0x400f3118u
#define CYREG_UDB_P0_ROUTE_HC25 0x400f3119u
#define CYREG_UDB_P0_ROUTE_HC26 0x400f311au
#define CYREG_UDB_P0_ROUTE_HC27 0x400f311bu
#define CYREG_UDB_P0_ROUTE_HC28 0x400f311cu
#define CYREG_UDB_P0_ROUTE_HC29 0x400f311du
#define CYREG_UDB_P0_ROUTE_HC30 0x400f311eu
#define CYREG_UDB_P0_ROUTE_HC31 0x400f311fu
#define CYREG_UDB_P0_ROUTE_HC32 0x400f3120u
#define CYREG_UDB_P0_ROUTE_HC33 0x400f3121u
#define CYREG_UDB_P0_ROUTE_HC34 0x400f3122u
#define CYREG_UDB_P0_ROUTE_HC35 0x400f3123u
#define CYREG_UDB_P0_ROUTE_HC36 0x400f3124u
#define CYREG_UDB_P0_ROUTE_HC37 0x400f3125u
#define CYREG_UDB_P0_ROUTE_HC38 0x400f3126u
#define CYREG_UDB_P0_ROUTE_HC39 0x400f3127u
#define CYREG_UDB_P0_ROUTE_HC40 0x400f3128u
#define CYREG_UDB_P0_ROUTE_HC41 0x400f3129u
#define CYREG_UDB_P0_ROUTE_HC42 0x400f312au
#define CYREG_UDB_P0_ROUTE_HC43 0x400f312bu
#define CYREG_UDB_P0_ROUTE_HC44 0x400f312cu
#define CYREG_UDB_P0_ROUTE_HC45 0x400f312du
#define CYREG_UDB_P0_ROUTE_HC46 0x400f312eu
#define CYREG_UDB_P0_ROUTE_HC47 0x400f312fu
#define CYREG_UDB_P0_ROUTE_HC48 0x400f3130u
#define CYREG_UDB_P0_ROUTE_HC49 0x400f3131u
#define CYREG_UDB_P0_ROUTE_HC50 0x400f3132u
#define CYREG_UDB_P0_ROUTE_HC51 0x400f3133u
#define CYREG_UDB_P0_ROUTE_HC52 0x400f3134u
#define CYREG_UDB_P0_ROUTE_HC53 0x400f3135u
#define CYREG_UDB_P0_ROUTE_HC54 0x400f3136u
#define CYREG_UDB_P0_ROUTE_HC55 0x400f3137u
#define CYREG_UDB_P0_ROUTE_HC56 0x400f3138u
#define CYREG_UDB_P0_ROUTE_HC57 0x400f3139u
#define CYREG_UDB_P0_ROUTE_HC58 0x400f313au
#define CYREG_UDB_P0_ROUTE_HC59 0x400f313bu
#define CYREG_UDB_P0_ROUTE_HC60 0x400f313cu
#define CYREG_UDB_P0_ROUTE_HC61 0x400f313du
#define CYREG_UDB_P0_ROUTE_HC62 0x400f313eu
#define CYREG_UDB_P0_ROUTE_HC63 0x400f313fu
#define CYREG_UDB_P0_ROUTE_HC64 0x400f3140u
#define CYREG_UDB_P0_ROUTE_HC65 0x400f3141u
#define CYREG_UDB_P0_ROUTE_HC66 0x400f3142u
#define CYREG_UDB_P0_ROUTE_HC67 0x400f3143u
#define CYREG_UDB_P0_ROUTE_HC68 0x400f3144u
#define CYREG_UDB_P0_ROUTE_HC69 0x400f3145u
#define CYREG_UDB_P0_ROUTE_HC70 0x400f3146u
#define CYREG_UDB_P0_ROUTE_HC71 0x400f3147u
#define CYREG_UDB_P0_ROUTE_HC72 0x400f3148u
#define CYREG_UDB_P0_ROUTE_HC73 0x400f3149u
#define CYREG_UDB_P0_ROUTE_HC74 0x400f314au
#define CYREG_UDB_P0_ROUTE_HC75 0x400f314bu
#define CYREG_UDB_P0_ROUTE_HC76 0x400f314cu
#define CYREG_UDB_P0_ROUTE_HC77 0x400f314du
#define CYREG_UDB_P0_ROUTE_HC78 0x400f314eu
#define CYREG_UDB_P0_ROUTE_HC79 0x400f314fu
#define CYREG_UDB_P0_ROUTE_HC80 0x400f3150u
#define CYREG_UDB_P0_ROUTE_HC81 0x400f3151u
#define CYREG_UDB_P0_ROUTE_HC82 0x400f3152u
#define CYREG_UDB_P0_ROUTE_HC83 0x400f3153u
#define CYREG_UDB_P0_ROUTE_HC84 0x400f3154u
#define CYREG_UDB_P0_ROUTE_HC85 0x400f3155u
#define CYREG_UDB_P0_ROUTE_HC86 0x400f3156u
#define CYREG_UDB_P0_ROUTE_HC87 0x400f3157u
#define CYREG_UDB_P0_ROUTE_HC88 0x400f3158u
#define CYREG_UDB_P0_ROUTE_HC89 0x400f3159u
#define CYREG_UDB_P0_ROUTE_HC90 0x400f315au
#define CYREG_UDB_P0_ROUTE_HC91 0x400f315bu
#define CYREG_UDB_P0_ROUTE_HC92 0x400f315cu
#define CYREG_UDB_P0_ROUTE_HC93 0x400f315du
#define CYREG_UDB_P0_ROUTE_HC94 0x400f315eu
#define CYREG_UDB_P0_ROUTE_HC95 0x400f315fu
#define CYREG_UDB_P0_ROUTE_HC96 0x400f3160u
#define CYREG_UDB_P0_ROUTE_HC97 0x400f3161u
#define CYREG_UDB_P0_ROUTE_HC98 0x400f3162u
#define CYREG_UDB_P0_ROUTE_HC99 0x400f3163u
#define CYREG_UDB_P0_ROUTE_HC100 0x400f3164u
#define CYREG_UDB_P0_ROUTE_HC101 0x400f3165u
#define CYREG_UDB_P0_ROUTE_HC102 0x400f3166u
#define CYREG_UDB_P0_ROUTE_HC103 0x400f3167u
#define CYREG_UDB_P0_ROUTE_HC104 0x400f3168u
#define CYREG_UDB_P0_ROUTE_HC105 0x400f3169u
#define CYREG_UDB_P0_ROUTE_HC106 0x400f316au
#define CYREG_UDB_P0_ROUTE_HC107 0x400f316bu
#define CYREG_UDB_P0_ROUTE_HC108 0x400f316cu
#define CYREG_UDB_P0_ROUTE_HC109 0x400f316du
#define CYREG_UDB_P0_ROUTE_HC110 0x400f316eu
#define CYREG_UDB_P0_ROUTE_HC111 0x400f316fu
#define CYREG_UDB_P0_ROUTE_HC112 0x400f3170u
#define CYREG_UDB_P0_ROUTE_HC113 0x400f3171u
#define CYREG_UDB_P0_ROUTE_HC114 0x400f3172u
#define CYREG_UDB_P0_ROUTE_HC115 0x400f3173u
#define CYREG_UDB_P0_ROUTE_HC116 0x400f3174u
#define CYREG_UDB_P0_ROUTE_HC117 0x400f3175u
#define CYREG_UDB_P0_ROUTE_HC118 0x400f3176u
#define CYREG_UDB_P0_ROUTE_HC119 0x400f3177u
#define CYREG_UDB_P0_ROUTE_HC120 0x400f3178u
#define CYREG_UDB_P0_ROUTE_HC121 0x400f3179u
#define CYREG_UDB_P0_ROUTE_HC122 0x400f317au
#define CYREG_UDB_P0_ROUTE_HC123 0x400f317bu
#define CYREG_UDB_P0_ROUTE_HC124 0x400f317cu
#define CYREG_UDB_P0_ROUTE_HC125 0x400f317du
#define CYREG_UDB_P0_ROUTE_HC126 0x400f317eu
#define CYREG_UDB_P0_ROUTE_HC127 0x400f317fu
#define CYREG_UDB_P0_ROUTE_HV_L0 0x400f3180u
#define CYFLD_UDB_P_ROUTE_HV_BYTE__OFFSET 0x00000000u
#define CYFLD_UDB_P_ROUTE_HV_BYTE__SIZE 0x00000008u
#define CYREG_UDB_P0_ROUTE_HV_L1 0x400f3181u
#define CYREG_UDB_P0_ROUTE_HV_L2 0x400f3182u
#define CYREG_UDB_P0_ROUTE_HV_L3 0x400f3183u
#define CYREG_UDB_P0_ROUTE_HV_L4 0x400f3184u
#define CYREG_UDB_P0_ROUTE_HV_L5 0x400f3185u
#define CYREG_UDB_P0_ROUTE_HV_L6 0x400f3186u
#define CYREG_UDB_P0_ROUTE_HV_L7 0x400f3187u
#define CYREG_UDB_P0_ROUTE_HV_L8 0x400f3188u
#define CYREG_UDB_P0_ROUTE_HV_L9 0x400f3189u
#define CYREG_UDB_P0_ROUTE_HV_L10 0x400f318au
#define CYREG_UDB_P0_ROUTE_HV_L11 0x400f318bu
#define CYREG_UDB_P0_ROUTE_HV_L12 0x400f318cu
#define CYREG_UDB_P0_ROUTE_HV_L13 0x400f318du
#define CYREG_UDB_P0_ROUTE_HV_L14 0x400f318eu
#define CYREG_UDB_P0_ROUTE_HV_L15 0x400f318fu
#define CYREG_UDB_P0_ROUTE_HS0 0x400f3190u
#define CYFLD_UDB_P_ROUTE_HS_BYTE__OFFSET 0x00000000u
#define CYFLD_UDB_P_ROUTE_HS_BYTE__SIZE 0x00000008u
#define CYREG_UDB_P0_ROUTE_HS1 0x400f3191u
#define CYREG_UDB_P0_ROUTE_HS2 0x400f3192u
#define CYREG_UDB_P0_ROUTE_HS3 0x400f3193u
#define CYREG_UDB_P0_ROUTE_HS4 0x400f3194u
#define CYREG_UDB_P0_ROUTE_HS5 0x400f3195u
#define CYREG_UDB_P0_ROUTE_HS6 0x400f3196u
#define CYREG_UDB_P0_ROUTE_HS7 0x400f3197u
#define CYREG_UDB_P0_ROUTE_HS8 0x400f3198u
#define CYREG_UDB_P0_ROUTE_HS9 0x400f3199u
#define CYREG_UDB_P0_ROUTE_HS10 0x400f319au
#define CYREG_UDB_P0_ROUTE_HS11 0x400f319bu
#define CYREG_UDB_P0_ROUTE_HS12 0x400f319cu
#define CYREG_UDB_P0_ROUTE_HS13 0x400f319du
#define CYREG_UDB_P0_ROUTE_HS14 0x400f319eu
#define CYREG_UDB_P0_ROUTE_HS15 0x400f319fu
#define CYREG_UDB_P0_ROUTE_HS16 0x400f31a0u
#define CYREG_UDB_P0_ROUTE_HS17 0x400f31a1u
#define CYREG_UDB_P0_ROUTE_HS18 0x400f31a2u
#define CYREG_UDB_P0_ROUTE_HS19 0x400f31a3u
#define CYREG_UDB_P0_ROUTE_HS20 0x400f31a4u
#define CYREG_UDB_P0_ROUTE_HS21 0x400f31a5u
#define CYREG_UDB_P0_ROUTE_HS22 0x400f31a6u
#define CYREG_UDB_P0_ROUTE_HS23 0x400f31a7u
#define CYREG_UDB_P0_ROUTE_HV_R0 0x400f31a8u
#define CYREG_UDB_P0_ROUTE_HV_R1 0x400f31a9u
#define CYREG_UDB_P0_ROUTE_HV_R2 0x400f31aau
#define CYREG_UDB_P0_ROUTE_HV_R3 0x400f31abu
#define CYREG_UDB_P0_ROUTE_HV_R4 0x400f31acu
#define CYREG_UDB_P0_ROUTE_HV_R5 0x400f31adu
#define CYREG_UDB_P0_ROUTE_HV_R6 0x400f31aeu
#define CYREG_UDB_P0_ROUTE_HV_R7 0x400f31afu
#define CYREG_UDB_P0_ROUTE_HV_R8 0x400f31b0u
#define CYREG_UDB_P0_ROUTE_HV_R9 0x400f31b1u
#define CYREG_UDB_P0_ROUTE_HV_R10 0x400f31b2u
#define CYREG_UDB_P0_ROUTE_HV_R11 0x400f31b3u
#define CYREG_UDB_P0_ROUTE_HV_R12 0x400f31b4u
#define CYREG_UDB_P0_ROUTE_HV_R13 0x400f31b5u
#define CYREG_UDB_P0_ROUTE_HV_R14 0x400f31b6u
#define CYREG_UDB_P0_ROUTE_HV_R15 0x400f31b7u
#define CYREG_UDB_P0_ROUTE_PLD0IN0 0x400f31c0u
#define CYFLD_UDB_P_ROUTE_PI_TOP__OFFSET 0x00000000u
#define CYFLD_UDB_P_ROUTE_PI_TOP__SIZE 0x00000004u
#define CYFLD_UDB_P_ROUTE_PI_BOT__OFFSET 0x00000004u
#define CYFLD_UDB_P_ROUTE_PI_BOT__SIZE 0x00000004u
#define CYREG_UDB_P0_ROUTE_PLD0IN1 0x400f31c2u
#define CYREG_UDB_P0_ROUTE_PLD0IN2 0x400f31c4u
#define CYREG_UDB_P0_ROUTE_PLD1IN0 0x400f31cau
#define CYREG_UDB_P0_ROUTE_PLD1IN1 0x400f31ccu
#define CYREG_UDB_P0_ROUTE_PLD1IN2 0x400f31ceu
#define CYREG_UDB_P0_ROUTE_DPIN0 0x400f31d0u
#define CYREG_UDB_P0_ROUTE_DPIN1 0x400f31d2u
#define CYFLD_UDB_P_ROUTE_PI_TOP2__OFFSET 0x00000002u
#define CYFLD_UDB_P_ROUTE_PI_TOP2__SIZE 0x00000002u
#define CYFLD_UDB_P_ROUTE_PI_BOT2__OFFSET 0x00000004u
#define CYFLD_UDB_P_ROUTE_PI_BOT2__SIZE 0x00000002u
#define CYREG_UDB_P0_ROUTE_SCIN 0x400f31d6u
#define CYREG_UDB_P0_ROUTE_SCIOIN 0x400f31d8u
#define CYREG_UDB_P0_ROUTE_RCIN 0x400f31deu
#define CYREG_UDB_P0_ROUTE_VS0 0x400f31e0u
#define CYFLD_UDB_P_ROUTE_VS_TOP__OFFSET 0x00000000u
#define CYFLD_UDB_P_ROUTE_VS_TOP__SIZE 0x00000004u
#define CYFLD_UDB_P_ROUTE_VS_BOT__OFFSET 0x00000004u
#define CYFLD_UDB_P_ROUTE_VS_BOT__SIZE 0x00000004u
#define CYREG_UDB_P0_ROUTE_VS1 0x400f31e2u
#define CYREG_UDB_P0_ROUTE_VS2 0x400f31e4u
#define CYREG_UDB_P0_ROUTE_VS3 0x400f31e6u
#define CYREG_UDB_P0_ROUTE_VS4 0x400f31e8u
#define CYREG_UDB_P0_ROUTE_VS5 0x400f31eau
#define CYREG_UDB_P0_ROUTE_VS6 0x400f31ecu
#define CYREG_UDB_P0_ROUTE_VS7 0x400f31eeu
#define CYDEV_UDB_P1_BASE 0x400f3200u
#define CYDEV_UDB_P1_SIZE 0x00000200u
#define CYDEV_UDB_P1_U0_BASE 0x400f3200u
#define CYDEV_UDB_P1_U0_SIZE 0x00000080u
#define CYREG_UDB_P1_U0_PLD_IT0 0x400f3200u
#define CYREG_UDB_P1_U0_PLD_IT1 0x400f3204u
#define CYREG_UDB_P1_U0_PLD_IT2 0x400f3208u
#define CYREG_UDB_P1_U0_PLD_IT3 0x400f320cu
#define CYREG_UDB_P1_U0_PLD_IT4 0x400f3210u
#define CYREG_UDB_P1_U0_PLD_IT5 0x400f3214u
#define CYREG_UDB_P1_U0_PLD_IT6 0x400f3218u
#define CYREG_UDB_P1_U0_PLD_IT7 0x400f321cu
#define CYREG_UDB_P1_U0_PLD_IT8 0x400f3220u
#define CYREG_UDB_P1_U0_PLD_IT9 0x400f3224u
#define CYREG_UDB_P1_U0_PLD_IT10 0x400f3228u
#define CYREG_UDB_P1_U0_PLD_IT11 0x400f322cu
#define CYREG_UDB_P1_U0_PLD_ORT0 0x400f3230u
#define CYREG_UDB_P1_U0_PLD_ORT1 0x400f3232u
#define CYREG_UDB_P1_U0_PLD_ORT2 0x400f3234u
#define CYREG_UDB_P1_U0_PLD_ORT3 0x400f3236u
#define CYREG_UDB_P1_U0_PLD_MC_CFG_CEN_CONST 0x400f3238u
#define CYREG_UDB_P1_U0_PLD_MC_CFG_XORFB 0x400f323au
#define CYREG_UDB_P1_U0_PLD_MC_SET_RESET 0x400f323cu
#define CYREG_UDB_P1_U0_PLD_MC_CFG_BYPASS 0x400f323eu
#define CYREG_UDB_P1_U0_CFG0 0x400f3240u
#define CYREG_UDB_P1_U0_CFG1 0x400f3241u
#define CYREG_UDB_P1_U0_CFG2 0x400f3242u
#define CYREG_UDB_P1_U0_CFG3 0x400f3243u
#define CYREG_UDB_P1_U0_CFG4 0x400f3244u
#define CYREG_UDB_P1_U0_CFG5 0x400f3245u
#define CYREG_UDB_P1_U0_CFG6 0x400f3246u
#define CYREG_UDB_P1_U0_CFG7 0x400f3247u
#define CYREG_UDB_P1_U0_CFG8 0x400f3248u
#define CYREG_UDB_P1_U0_CFG9 0x400f3249u
#define CYREG_UDB_P1_U0_CFG10 0x400f324au
#define CYREG_UDB_P1_U0_CFG11 0x400f324bu
#define CYREG_UDB_P1_U0_CFG12 0x400f324cu
#define CYREG_UDB_P1_U0_CFG13 0x400f324du
#define CYREG_UDB_P1_U0_CFG14 0x400f324eu
#define CYREG_UDB_P1_U0_CFG15 0x400f324fu
#define CYREG_UDB_P1_U0_CFG16 0x400f3250u
#define CYREG_UDB_P1_U0_CFG17 0x400f3251u
#define CYREG_UDB_P1_U0_CFG18 0x400f3252u
#define CYREG_UDB_P1_U0_CFG19 0x400f3253u
#define CYREG_UDB_P1_U0_CFG20 0x400f3254u
#define CYREG_UDB_P1_U0_CFG21 0x400f3255u
#define CYREG_UDB_P1_U0_CFG22 0x400f3256u
#define CYREG_UDB_P1_U0_CFG23 0x400f3257u
#define CYREG_UDB_P1_U0_CFG24 0x400f3258u
#define CYREG_UDB_P1_U0_CFG25 0x400f3259u
#define CYREG_UDB_P1_U0_CFG26 0x400f325au
#define CYREG_UDB_P1_U0_CFG27 0x400f325bu
#define CYREG_UDB_P1_U0_CFG28 0x400f325cu
#define CYREG_UDB_P1_U0_CFG29 0x400f325du
#define CYREG_UDB_P1_U0_CFG30 0x400f325eu
#define CYREG_UDB_P1_U0_CFG31 0x400f325fu
#define CYREG_UDB_P1_U0_DCFG0 0x400f3260u
#define CYREG_UDB_P1_U0_DCFG1 0x400f3262u
#define CYREG_UDB_P1_U0_DCFG2 0x400f3264u
#define CYREG_UDB_P1_U0_DCFG3 0x400f3266u
#define CYREG_UDB_P1_U0_DCFG4 0x400f3268u
#define CYREG_UDB_P1_U0_DCFG5 0x400f326au
#define CYREG_UDB_P1_U0_DCFG6 0x400f326cu
#define CYREG_UDB_P1_U0_DCFG7 0x400f326eu
#define CYDEV_UDB_P1_U1_BASE 0x400f3280u
#define CYDEV_UDB_P1_U1_SIZE 0x00000080u
#define CYREG_UDB_P1_U1_PLD_IT0 0x400f3280u
#define CYREG_UDB_P1_U1_PLD_IT1 0x400f3284u
#define CYREG_UDB_P1_U1_PLD_IT2 0x400f3288u
#define CYREG_UDB_P1_U1_PLD_IT3 0x400f328cu
#define CYREG_UDB_P1_U1_PLD_IT4 0x400f3290u
#define CYREG_UDB_P1_U1_PLD_IT5 0x400f3294u
#define CYREG_UDB_P1_U1_PLD_IT6 0x400f3298u
#define CYREG_UDB_P1_U1_PLD_IT7 0x400f329cu
#define CYREG_UDB_P1_U1_PLD_IT8 0x400f32a0u
#define CYREG_UDB_P1_U1_PLD_IT9 0x400f32a4u
#define CYREG_UDB_P1_U1_PLD_IT10 0x400f32a8u
#define CYREG_UDB_P1_U1_PLD_IT11 0x400f32acu
#define CYREG_UDB_P1_U1_PLD_ORT0 0x400f32b0u
#define CYREG_UDB_P1_U1_PLD_ORT1 0x400f32b2u
#define CYREG_UDB_P1_U1_PLD_ORT2 0x400f32b4u
#define CYREG_UDB_P1_U1_PLD_ORT3 0x400f32b6u
#define CYREG_UDB_P1_U1_PLD_MC_CFG_CEN_CONST 0x400f32b8u
#define CYREG_UDB_P1_U1_PLD_MC_CFG_XORFB 0x400f32bau
#define CYREG_UDB_P1_U1_PLD_MC_SET_RESET 0x400f32bcu
#define CYREG_UDB_P1_U1_PLD_MC_CFG_BYPASS 0x400f32beu
#define CYREG_UDB_P1_U1_CFG0 0x400f32c0u
#define CYREG_UDB_P1_U1_CFG1 0x400f32c1u
#define CYREG_UDB_P1_U1_CFG2 0x400f32c2u
#define CYREG_UDB_P1_U1_CFG3 0x400f32c3u
#define CYREG_UDB_P1_U1_CFG4 0x400f32c4u
#define CYREG_UDB_P1_U1_CFG5 0x400f32c5u
#define CYREG_UDB_P1_U1_CFG6 0x400f32c6u
#define CYREG_UDB_P1_U1_CFG7 0x400f32c7u
#define CYREG_UDB_P1_U1_CFG8 0x400f32c8u
#define CYREG_UDB_P1_U1_CFG9 0x400f32c9u
#define CYREG_UDB_P1_U1_CFG10 0x400f32cau
#define CYREG_UDB_P1_U1_CFG11 0x400f32cbu
#define CYREG_UDB_P1_U1_CFG12 0x400f32ccu
#define CYREG_UDB_P1_U1_CFG13 0x400f32cdu
#define CYREG_UDB_P1_U1_CFG14 0x400f32ceu
#define CYREG_UDB_P1_U1_CFG15 0x400f32cfu
#define CYREG_UDB_P1_U1_CFG16 0x400f32d0u
#define CYREG_UDB_P1_U1_CFG17 0x400f32d1u
#define CYREG_UDB_P1_U1_CFG18 0x400f32d2u
#define CYREG_UDB_P1_U1_CFG19 0x400f32d3u
#define CYREG_UDB_P1_U1_CFG20 0x400f32d4u
#define CYREG_UDB_P1_U1_CFG21 0x400f32d5u
#define CYREG_UDB_P1_U1_CFG22 0x400f32d6u
#define CYREG_UDB_P1_U1_CFG23 0x400f32d7u
#define CYREG_UDB_P1_U1_CFG24 0x400f32d8u
#define CYREG_UDB_P1_U1_CFG25 0x400f32d9u
#define CYREG_UDB_P1_U1_CFG26 0x400f32dau
#define CYREG_UDB_P1_U1_CFG27 0x400f32dbu
#define CYREG_UDB_P1_U1_CFG28 0x400f32dcu
#define CYREG_UDB_P1_U1_CFG29 0x400f32ddu
#define CYREG_UDB_P1_U1_CFG30 0x400f32deu
#define CYREG_UDB_P1_U1_CFG31 0x400f32dfu
#define CYREG_UDB_P1_U1_DCFG0 0x400f32e0u
#define CYREG_UDB_P1_U1_DCFG1 0x400f32e2u
#define CYREG_UDB_P1_U1_DCFG2 0x400f32e4u
#define CYREG_UDB_P1_U1_DCFG3 0x400f32e6u
#define CYREG_UDB_P1_U1_DCFG4 0x400f32e8u
#define CYREG_UDB_P1_U1_DCFG5 0x400f32eau
#define CYREG_UDB_P1_U1_DCFG6 0x400f32ecu
#define CYREG_UDB_P1_U1_DCFG7 0x400f32eeu
#define CYDEV_UDB_P1_ROUTE_BASE 0x400f3300u
#define CYDEV_UDB_P1_ROUTE_SIZE 0x00000100u
#define CYREG_UDB_P1_ROUTE_HC0 0x400f3300u
#define CYREG_UDB_P1_ROUTE_HC1 0x400f3301u
#define CYREG_UDB_P1_ROUTE_HC2 0x400f3302u
#define CYREG_UDB_P1_ROUTE_HC3 0x400f3303u
#define CYREG_UDB_P1_ROUTE_HC4 0x400f3304u
#define CYREG_UDB_P1_ROUTE_HC5 0x400f3305u
#define CYREG_UDB_P1_ROUTE_HC6 0x400f3306u
#define CYREG_UDB_P1_ROUTE_HC7 0x400f3307u
#define CYREG_UDB_P1_ROUTE_HC8 0x400f3308u
#define CYREG_UDB_P1_ROUTE_HC9 0x400f3309u
#define CYREG_UDB_P1_ROUTE_HC10 0x400f330au
#define CYREG_UDB_P1_ROUTE_HC11 0x400f330bu
#define CYREG_UDB_P1_ROUTE_HC12 0x400f330cu
#define CYREG_UDB_P1_ROUTE_HC13 0x400f330du
#define CYREG_UDB_P1_ROUTE_HC14 0x400f330eu
#define CYREG_UDB_P1_ROUTE_HC15 0x400f330fu
#define CYREG_UDB_P1_ROUTE_HC16 0x400f3310u
#define CYREG_UDB_P1_ROUTE_HC17 0x400f3311u
#define CYREG_UDB_P1_ROUTE_HC18 0x400f3312u
#define CYREG_UDB_P1_ROUTE_HC19 0x400f3313u
#define CYREG_UDB_P1_ROUTE_HC20 0x400f3314u
#define CYREG_UDB_P1_ROUTE_HC21 0x400f3315u
#define CYREG_UDB_P1_ROUTE_HC22 0x400f3316u
#define CYREG_UDB_P1_ROUTE_HC23 0x400f3317u
#define CYREG_UDB_P1_ROUTE_HC24 0x400f3318u
#define CYREG_UDB_P1_ROUTE_HC25 0x400f3319u
#define CYREG_UDB_P1_ROUTE_HC26 0x400f331au
#define CYREG_UDB_P1_ROUTE_HC27 0x400f331bu
#define CYREG_UDB_P1_ROUTE_HC28 0x400f331cu
#define CYREG_UDB_P1_ROUTE_HC29 0x400f331du
#define CYREG_UDB_P1_ROUTE_HC30 0x400f331eu
#define CYREG_UDB_P1_ROUTE_HC31 0x400f331fu
#define CYREG_UDB_P1_ROUTE_HC32 0x400f3320u
#define CYREG_UDB_P1_ROUTE_HC33 0x400f3321u
#define CYREG_UDB_P1_ROUTE_HC34 0x400f3322u
#define CYREG_UDB_P1_ROUTE_HC35 0x400f3323u
#define CYREG_UDB_P1_ROUTE_HC36 0x400f3324u
#define CYREG_UDB_P1_ROUTE_HC37 0x400f3325u
#define CYREG_UDB_P1_ROUTE_HC38 0x400f3326u
#define CYREG_UDB_P1_ROUTE_HC39 0x400f3327u
#define CYREG_UDB_P1_ROUTE_HC40 0x400f3328u
#define CYREG_UDB_P1_ROUTE_HC41 0x400f3329u
#define CYREG_UDB_P1_ROUTE_HC42 0x400f332au
#define CYREG_UDB_P1_ROUTE_HC43 0x400f332bu
#define CYREG_UDB_P1_ROUTE_HC44 0x400f332cu
#define CYREG_UDB_P1_ROUTE_HC45 0x400f332du
#define CYREG_UDB_P1_ROUTE_HC46 0x400f332eu
#define CYREG_UDB_P1_ROUTE_HC47 0x400f332fu
#define CYREG_UDB_P1_ROUTE_HC48 0x400f3330u
#define CYREG_UDB_P1_ROUTE_HC49 0x400f3331u
#define CYREG_UDB_P1_ROUTE_HC50 0x400f3332u
#define CYREG_UDB_P1_ROUTE_HC51 0x400f3333u
#define CYREG_UDB_P1_ROUTE_HC52 0x400f3334u
#define CYREG_UDB_P1_ROUTE_HC53 0x400f3335u
#define CYREG_UDB_P1_ROUTE_HC54 0x400f3336u
#define CYREG_UDB_P1_ROUTE_HC55 0x400f3337u
#define CYREG_UDB_P1_ROUTE_HC56 0x400f3338u
#define CYREG_UDB_P1_ROUTE_HC57 0x400f3339u
#define CYREG_UDB_P1_ROUTE_HC58 0x400f333au
#define CYREG_UDB_P1_ROUTE_HC59 0x400f333bu
#define CYREG_UDB_P1_ROUTE_HC60 0x400f333cu
#define CYREG_UDB_P1_ROUTE_HC61 0x400f333du
#define CYREG_UDB_P1_ROUTE_HC62 0x400f333eu
#define CYREG_UDB_P1_ROUTE_HC63 0x400f333fu
#define CYREG_UDB_P1_ROUTE_HC64 0x400f3340u
#define CYREG_UDB_P1_ROUTE_HC65 0x400f3341u
#define CYREG_UDB_P1_ROUTE_HC66 0x400f3342u
#define CYREG_UDB_P1_ROUTE_HC67 0x400f3343u
#define CYREG_UDB_P1_ROUTE_HC68 0x400f3344u
#define CYREG_UDB_P1_ROUTE_HC69 0x400f3345u
#define CYREG_UDB_P1_ROUTE_HC70 0x400f3346u
#define CYREG_UDB_P1_ROUTE_HC71 0x400f3347u
#define CYREG_UDB_P1_ROUTE_HC72 0x400f3348u
#define CYREG_UDB_P1_ROUTE_HC73 0x400f3349u
#define CYREG_UDB_P1_ROUTE_HC74 0x400f334au
#define CYREG_UDB_P1_ROUTE_HC75 0x400f334bu
#define CYREG_UDB_P1_ROUTE_HC76 0x400f334cu
#define CYREG_UDB_P1_ROUTE_HC77 0x400f334du
#define CYREG_UDB_P1_ROUTE_HC78 0x400f334eu
#define CYREG_UDB_P1_ROUTE_HC79 0x400f334fu
#define CYREG_UDB_P1_ROUTE_HC80 0x400f3350u
#define CYREG_UDB_P1_ROUTE_HC81 0x400f3351u
#define CYREG_UDB_P1_ROUTE_HC82 0x400f3352u
#define CYREG_UDB_P1_ROUTE_HC83 0x400f3353u
#define CYREG_UDB_P1_ROUTE_HC84 0x400f3354u
#define CYREG_UDB_P1_ROUTE_HC85 0x400f3355u
#define CYREG_UDB_P1_ROUTE_HC86 0x400f3356u
#define CYREG_UDB_P1_ROUTE_HC87 0x400f3357u
#define CYREG_UDB_P1_ROUTE_HC88 0x400f3358u
#define CYREG_UDB_P1_ROUTE_HC89 0x400f3359u
#define CYREG_UDB_P1_ROUTE_HC90 0x400f335au
#define CYREG_UDB_P1_ROUTE_HC91 0x400f335bu
#define CYREG_UDB_P1_ROUTE_HC92 0x400f335cu
#define CYREG_UDB_P1_ROUTE_HC93 0x400f335du
#define CYREG_UDB_P1_ROUTE_HC94 0x400f335eu
#define CYREG_UDB_P1_ROUTE_HC95 0x400f335fu
#define CYREG_UDB_P1_ROUTE_HC96 0x400f3360u
#define CYREG_UDB_P1_ROUTE_HC97 0x400f3361u
#define CYREG_UDB_P1_ROUTE_HC98 0x400f3362u
#define CYREG_UDB_P1_ROUTE_HC99 0x400f3363u
#define CYREG_UDB_P1_ROUTE_HC100 0x400f3364u
#define CYREG_UDB_P1_ROUTE_HC101 0x400f3365u
#define CYREG_UDB_P1_ROUTE_HC102 0x400f3366u
#define CYREG_UDB_P1_ROUTE_HC103 0x400f3367u
#define CYREG_UDB_P1_ROUTE_HC104 0x400f3368u
#define CYREG_UDB_P1_ROUTE_HC105 0x400f3369u
#define CYREG_UDB_P1_ROUTE_HC106 0x400f336au
#define CYREG_UDB_P1_ROUTE_HC107 0x400f336bu
#define CYREG_UDB_P1_ROUTE_HC108 0x400f336cu
#define CYREG_UDB_P1_ROUTE_HC109 0x400f336du
#define CYREG_UDB_P1_ROUTE_HC110 0x400f336eu
#define CYREG_UDB_P1_ROUTE_HC111 0x400f336fu
#define CYREG_UDB_P1_ROUTE_HC112 0x400f3370u
#define CYREG_UDB_P1_ROUTE_HC113 0x400f3371u
#define CYREG_UDB_P1_ROUTE_HC114 0x400f3372u
#define CYREG_UDB_P1_ROUTE_HC115 0x400f3373u
#define CYREG_UDB_P1_ROUTE_HC116 0x400f3374u
#define CYREG_UDB_P1_ROUTE_HC117 0x400f3375u
#define CYREG_UDB_P1_ROUTE_HC118 0x400f3376u
#define CYREG_UDB_P1_ROUTE_HC119 0x400f3377u
#define CYREG_UDB_P1_ROUTE_HC120 0x400f3378u
#define CYREG_UDB_P1_ROUTE_HC121 0x400f3379u
#define CYREG_UDB_P1_ROUTE_HC122 0x400f337au
#define CYREG_UDB_P1_ROUTE_HC123 0x400f337bu
#define CYREG_UDB_P1_ROUTE_HC124 0x400f337cu
#define CYREG_UDB_P1_ROUTE_HC125 0x400f337du
#define CYREG_UDB_P1_ROUTE_HC126 0x400f337eu
#define CYREG_UDB_P1_ROUTE_HC127 0x400f337fu
#define CYREG_UDB_P1_ROUTE_HV_L0 0x400f3380u
#define CYREG_UDB_P1_ROUTE_HV_L1 0x400f3381u
#define CYREG_UDB_P1_ROUTE_HV_L2 0x400f3382u
#define CYREG_UDB_P1_ROUTE_HV_L3 0x400f3383u
#define CYREG_UDB_P1_ROUTE_HV_L4 0x400f3384u
#define CYREG_UDB_P1_ROUTE_HV_L5 0x400f3385u
#define CYREG_UDB_P1_ROUTE_HV_L6 0x400f3386u
#define CYREG_UDB_P1_ROUTE_HV_L7 0x400f3387u
#define CYREG_UDB_P1_ROUTE_HV_L8 0x400f3388u
#define CYREG_UDB_P1_ROUTE_HV_L9 0x400f3389u
#define CYREG_UDB_P1_ROUTE_HV_L10 0x400f338au
#define CYREG_UDB_P1_ROUTE_HV_L11 0x400f338bu
#define CYREG_UDB_P1_ROUTE_HV_L12 0x400f338cu
#define CYREG_UDB_P1_ROUTE_HV_L13 0x400f338du
#define CYREG_UDB_P1_ROUTE_HV_L14 0x400f338eu
#define CYREG_UDB_P1_ROUTE_HV_L15 0x400f338fu
#define CYREG_UDB_P1_ROUTE_HS0 0x400f3390u
#define CYREG_UDB_P1_ROUTE_HS1 0x400f3391u
#define CYREG_UDB_P1_ROUTE_HS2 0x400f3392u
#define CYREG_UDB_P1_ROUTE_HS3 0x400f3393u
#define CYREG_UDB_P1_ROUTE_HS4 0x400f3394u
#define CYREG_UDB_P1_ROUTE_HS5 0x400f3395u
#define CYREG_UDB_P1_ROUTE_HS6 0x400f3396u
#define CYREG_UDB_P1_ROUTE_HS7 0x400f3397u
#define CYREG_UDB_P1_ROUTE_HS8 0x400f3398u
#define CYREG_UDB_P1_ROUTE_HS9 0x400f3399u
#define CYREG_UDB_P1_ROUTE_HS10 0x400f339au
#define CYREG_UDB_P1_ROUTE_HS11 0x400f339bu
#define CYREG_UDB_P1_ROUTE_HS12 0x400f339cu
#define CYREG_UDB_P1_ROUTE_HS13 0x400f339du
#define CYREG_UDB_P1_ROUTE_HS14 0x400f339eu
#define CYREG_UDB_P1_ROUTE_HS15 0x400f339fu
#define CYREG_UDB_P1_ROUTE_HS16 0x400f33a0u
#define CYREG_UDB_P1_ROUTE_HS17 0x400f33a1u
#define CYREG_UDB_P1_ROUTE_HS18 0x400f33a2u
#define CYREG_UDB_P1_ROUTE_HS19 0x400f33a3u
#define CYREG_UDB_P1_ROUTE_HS20 0x400f33a4u
#define CYREG_UDB_P1_ROUTE_HS21 0x400f33a5u
#define CYREG_UDB_P1_ROUTE_HS22 0x400f33a6u
#define CYREG_UDB_P1_ROUTE_HS23 0x400f33a7u
#define CYREG_UDB_P1_ROUTE_HV_R0 0x400f33a8u
#define CYREG_UDB_P1_ROUTE_HV_R1 0x400f33a9u
#define CYREG_UDB_P1_ROUTE_HV_R2 0x400f33aau
#define CYREG_UDB_P1_ROUTE_HV_R3 0x400f33abu
#define CYREG_UDB_P1_ROUTE_HV_R4 0x400f33acu
#define CYREG_UDB_P1_ROUTE_HV_R5 0x400f33adu
#define CYREG_UDB_P1_ROUTE_HV_R6 0x400f33aeu
#define CYREG_UDB_P1_ROUTE_HV_R7 0x400f33afu
#define CYREG_UDB_P1_ROUTE_HV_R8 0x400f33b0u
#define CYREG_UDB_P1_ROUTE_HV_R9 0x400f33b1u
#define CYREG_UDB_P1_ROUTE_HV_R10 0x400f33b2u
#define CYREG_UDB_P1_ROUTE_HV_R11 0x400f33b3u
#define CYREG_UDB_P1_ROUTE_HV_R12 0x400f33b4u
#define CYREG_UDB_P1_ROUTE_HV_R13 0x400f33b5u
#define CYREG_UDB_P1_ROUTE_HV_R14 0x400f33b6u
#define CYREG_UDB_P1_ROUTE_HV_R15 0x400f33b7u
#define CYREG_UDB_P1_ROUTE_PLD0IN0 0x400f33c0u
#define CYREG_UDB_P1_ROUTE_PLD0IN1 0x400f33c2u
#define CYREG_UDB_P1_ROUTE_PLD0IN2 0x400f33c4u
#define CYREG_UDB_P1_ROUTE_PLD1IN0 0x400f33cau
#define CYREG_UDB_P1_ROUTE_PLD1IN1 0x400f33ccu
#define CYREG_UDB_P1_ROUTE_PLD1IN2 0x400f33ceu
#define CYREG_UDB_P1_ROUTE_DPIN0 0x400f33d0u
#define CYREG_UDB_P1_ROUTE_DPIN1 0x400f33d2u
#define CYREG_UDB_P1_ROUTE_SCIN 0x400f33d6u
#define CYREG_UDB_P1_ROUTE_SCIOIN 0x400f33d8u
#define CYREG_UDB_P1_ROUTE_RCIN 0x400f33deu
#define CYREG_UDB_P1_ROUTE_VS0 0x400f33e0u
#define CYREG_UDB_P1_ROUTE_VS1 0x400f33e2u
#define CYREG_UDB_P1_ROUTE_VS2 0x400f33e4u
#define CYREG_UDB_P1_ROUTE_VS3 0x400f33e6u
#define CYREG_UDB_P1_ROUTE_VS4 0x400f33e8u
#define CYREG_UDB_P1_ROUTE_VS5 0x400f33eau
#define CYREG_UDB_P1_ROUTE_VS6 0x400f33ecu
#define CYREG_UDB_P1_ROUTE_VS7 0x400f33eeu
#define CYDEV_UDB_DSI0_BASE 0x400f4000u
#define CYDEV_UDB_DSI0_SIZE 0x00000100u
#define CYREG_UDB_DSI0_HC0 0x400f4000u
#define CYFLD_UDB_DSI_HC_BYTE__OFFSET 0x00000000u
#define CYFLD_UDB_DSI_HC_BYTE__SIZE 0x00000008u
#define CYREG_UDB_DSI0_HC1 0x400f4001u
#define CYREG_UDB_DSI0_HC2 0x400f4002u
#define CYREG_UDB_DSI0_HC3 0x400f4003u
#define CYREG_UDB_DSI0_HC4 0x400f4004u
#define CYREG_UDB_DSI0_HC5 0x400f4005u
#define CYREG_UDB_DSI0_HC6 0x400f4006u
#define CYREG_UDB_DSI0_HC7 0x400f4007u
#define CYREG_UDB_DSI0_HC8 0x400f4008u
#define CYREG_UDB_DSI0_HC9 0x400f4009u
#define CYREG_UDB_DSI0_HC10 0x400f400au
#define CYREG_UDB_DSI0_HC11 0x400f400bu
#define CYREG_UDB_DSI0_HC12 0x400f400cu
#define CYREG_UDB_DSI0_HC13 0x400f400du
#define CYREG_UDB_DSI0_HC14 0x400f400eu
#define CYREG_UDB_DSI0_HC15 0x400f400fu
#define CYREG_UDB_DSI0_HC16 0x400f4010u
#define CYREG_UDB_DSI0_HC17 0x400f4011u
#define CYREG_UDB_DSI0_HC18 0x400f4012u
#define CYREG_UDB_DSI0_HC19 0x400f4013u
#define CYREG_UDB_DSI0_HC20 0x400f4014u
#define CYREG_UDB_DSI0_HC21 0x400f4015u
#define CYREG_UDB_DSI0_HC22 0x400f4016u
#define CYREG_UDB_DSI0_HC23 0x400f4017u
#define CYREG_UDB_DSI0_HC24 0x400f4018u
#define CYREG_UDB_DSI0_HC25 0x400f4019u
#define CYREG_UDB_DSI0_HC26 0x400f401au
#define CYREG_UDB_DSI0_HC27 0x400f401bu
#define CYREG_UDB_DSI0_HC28 0x400f401cu
#define CYREG_UDB_DSI0_HC29 0x400f401du
#define CYREG_UDB_DSI0_HC30 0x400f401eu
#define CYREG_UDB_DSI0_HC31 0x400f401fu
#define CYREG_UDB_DSI0_HC32 0x400f4020u
#define CYREG_UDB_DSI0_HC33 0x400f4021u
#define CYREG_UDB_DSI0_HC34 0x400f4022u
#define CYREG_UDB_DSI0_HC35 0x400f4023u
#define CYREG_UDB_DSI0_HC36 0x400f4024u
#define CYREG_UDB_DSI0_HC37 0x400f4025u
#define CYREG_UDB_DSI0_HC38 0x400f4026u
#define CYREG_UDB_DSI0_HC39 0x400f4027u
#define CYREG_UDB_DSI0_HC40 0x400f4028u
#define CYREG_UDB_DSI0_HC41 0x400f4029u
#define CYREG_UDB_DSI0_HC42 0x400f402au
#define CYREG_UDB_DSI0_HC43 0x400f402bu
#define CYREG_UDB_DSI0_HC44 0x400f402cu
#define CYREG_UDB_DSI0_HC45 0x400f402du
#define CYREG_UDB_DSI0_HC46 0x400f402eu
#define CYREG_UDB_DSI0_HC47 0x400f402fu
#define CYREG_UDB_DSI0_HC48 0x400f4030u
#define CYREG_UDB_DSI0_HC49 0x400f4031u
#define CYREG_UDB_DSI0_HC50 0x400f4032u
#define CYREG_UDB_DSI0_HC51 0x400f4033u
#define CYREG_UDB_DSI0_HC52 0x400f4034u
#define CYREG_UDB_DSI0_HC53 0x400f4035u
#define CYREG_UDB_DSI0_HC54 0x400f4036u
#define CYREG_UDB_DSI0_HC55 0x400f4037u
#define CYREG_UDB_DSI0_HC56 0x400f4038u
#define CYREG_UDB_DSI0_HC57 0x400f4039u
#define CYREG_UDB_DSI0_HC58 0x400f403au
#define CYREG_UDB_DSI0_HC59 0x400f403bu
#define CYREG_UDB_DSI0_HC60 0x400f403cu
#define CYREG_UDB_DSI0_HC61 0x400f403du
#define CYREG_UDB_DSI0_HC62 0x400f403eu
#define CYREG_UDB_DSI0_HC63 0x400f403fu
#define CYREG_UDB_DSI0_HC64 0x400f4040u
#define CYREG_UDB_DSI0_HC65 0x400f4041u
#define CYREG_UDB_DSI0_HC66 0x400f4042u
#define CYREG_UDB_DSI0_HC67 0x400f4043u
#define CYREG_UDB_DSI0_HC68 0x400f4044u
#define CYREG_UDB_DSI0_HC69 0x400f4045u
#define CYREG_UDB_DSI0_HC70 0x400f4046u
#define CYREG_UDB_DSI0_HC71 0x400f4047u
#define CYREG_UDB_DSI0_HC72 0x400f4048u
#define CYREG_UDB_DSI0_HC73 0x400f4049u
#define CYREG_UDB_DSI0_HC74 0x400f404au
#define CYREG_UDB_DSI0_HC75 0x400f404bu
#define CYREG_UDB_DSI0_HC76 0x400f404cu
#define CYREG_UDB_DSI0_HC77 0x400f404du
#define CYREG_UDB_DSI0_HC78 0x400f404eu
#define CYREG_UDB_DSI0_HC79 0x400f404fu
#define CYREG_UDB_DSI0_HC80 0x400f4050u
#define CYREG_UDB_DSI0_HC81 0x400f4051u
#define CYREG_UDB_DSI0_HC82 0x400f4052u
#define CYREG_UDB_DSI0_HC83 0x400f4053u
#define CYREG_UDB_DSI0_HC84 0x400f4054u
#define CYREG_UDB_DSI0_HC85 0x400f4055u
#define CYREG_UDB_DSI0_HC86 0x400f4056u
#define CYREG_UDB_DSI0_HC87 0x400f4057u
#define CYREG_UDB_DSI0_HC88 0x400f4058u
#define CYREG_UDB_DSI0_HC89 0x400f4059u
#define CYREG_UDB_DSI0_HC90 0x400f405au
#define CYREG_UDB_DSI0_HC91 0x400f405bu
#define CYREG_UDB_DSI0_HC92 0x400f405cu
#define CYREG_UDB_DSI0_HC93 0x400f405du
#define CYREG_UDB_DSI0_HC94 0x400f405eu
#define CYREG_UDB_DSI0_HC95 0x400f405fu
#define CYREG_UDB_DSI0_HC96 0x400f4060u
#define CYREG_UDB_DSI0_HC97 0x400f4061u
#define CYREG_UDB_DSI0_HC98 0x400f4062u
#define CYREG_UDB_DSI0_HC99 0x400f4063u
#define CYREG_UDB_DSI0_HC100 0x400f4064u
#define CYREG_UDB_DSI0_HC101 0x400f4065u
#define CYREG_UDB_DSI0_HC102 0x400f4066u
#define CYREG_UDB_DSI0_HC103 0x400f4067u
#define CYREG_UDB_DSI0_HC104 0x400f4068u
#define CYREG_UDB_DSI0_HC105 0x400f4069u
#define CYREG_UDB_DSI0_HC106 0x400f406au
#define CYREG_UDB_DSI0_HC107 0x400f406bu
#define CYREG_UDB_DSI0_HC108 0x400f406cu
#define CYREG_UDB_DSI0_HC109 0x400f406du
#define CYREG_UDB_DSI0_HC110 0x400f406eu
#define CYREG_UDB_DSI0_HC111 0x400f406fu
#define CYREG_UDB_DSI0_HC112 0x400f4070u
#define CYREG_UDB_DSI0_HC113 0x400f4071u
#define CYREG_UDB_DSI0_HC114 0x400f4072u
#define CYREG_UDB_DSI0_HC115 0x400f4073u
#define CYREG_UDB_DSI0_HC116 0x400f4074u
#define CYREG_UDB_DSI0_HC117 0x400f4075u
#define CYREG_UDB_DSI0_HC118 0x400f4076u
#define CYREG_UDB_DSI0_HC119 0x400f4077u
#define CYREG_UDB_DSI0_HC120 0x400f4078u
#define CYREG_UDB_DSI0_HC121 0x400f4079u
#define CYREG_UDB_DSI0_HC122 0x400f407au
#define CYREG_UDB_DSI0_HC123 0x400f407bu
#define CYREG_UDB_DSI0_HC124 0x400f407cu
#define CYREG_UDB_DSI0_HC125 0x400f407du
#define CYREG_UDB_DSI0_HC126 0x400f407eu
#define CYREG_UDB_DSI0_HC127 0x400f407fu
#define CYREG_UDB_DSI0_HV_L0 0x400f4080u
#define CYFLD_UDB_DSI_HV_BYTE__OFFSET 0x00000000u
#define CYFLD_UDB_DSI_HV_BYTE__SIZE 0x00000008u
#define CYREG_UDB_DSI0_HV_L1 0x400f4081u
#define CYREG_UDB_DSI0_HV_L2 0x400f4082u
#define CYREG_UDB_DSI0_HV_L3 0x400f4083u
#define CYREG_UDB_DSI0_HV_L4 0x400f4084u
#define CYREG_UDB_DSI0_HV_L5 0x400f4085u
#define CYREG_UDB_DSI0_HV_L6 0x400f4086u
#define CYREG_UDB_DSI0_HV_L7 0x400f4087u
#define CYREG_UDB_DSI0_HV_L8 0x400f4088u
#define CYREG_UDB_DSI0_HV_L9 0x400f4089u
#define CYREG_UDB_DSI0_HV_L10 0x400f408au
#define CYREG_UDB_DSI0_HV_L11 0x400f408bu
#define CYREG_UDB_DSI0_HV_L12 0x400f408cu
#define CYREG_UDB_DSI0_HV_L13 0x400f408du
#define CYREG_UDB_DSI0_HV_L14 0x400f408eu
#define CYREG_UDB_DSI0_HV_L15 0x400f408fu
#define CYREG_UDB_DSI0_HS0 0x400f4090u
#define CYFLD_UDB_DSI_HS_BYTE__OFFSET 0x00000000u
#define CYFLD_UDB_DSI_HS_BYTE__SIZE 0x00000008u
#define CYREG_UDB_DSI0_HS1 0x400f4091u
#define CYREG_UDB_DSI0_HS2 0x400f4092u
#define CYREG_UDB_DSI0_HS3 0x400f4093u
#define CYREG_UDB_DSI0_HS4 0x400f4094u
#define CYREG_UDB_DSI0_HS5 0x400f4095u
#define CYREG_UDB_DSI0_HS6 0x400f4096u
#define CYREG_UDB_DSI0_HS7 0x400f4097u
#define CYREG_UDB_DSI0_HS8 0x400f4098u
#define CYREG_UDB_DSI0_HS9 0x400f4099u
#define CYREG_UDB_DSI0_HS10 0x400f409au
#define CYREG_UDB_DSI0_HS11 0x400f409bu
#define CYREG_UDB_DSI0_HS12 0x400f409cu
#define CYREG_UDB_DSI0_HS13 0x400f409du
#define CYREG_UDB_DSI0_HS14 0x400f409eu
#define CYREG_UDB_DSI0_HS15 0x400f409fu
#define CYREG_UDB_DSI0_HS16 0x400f40a0u
#define CYREG_UDB_DSI0_HS17 0x400f40a1u
#define CYREG_UDB_DSI0_HS18 0x400f40a2u
#define CYREG_UDB_DSI0_HS19 0x400f40a3u
#define CYREG_UDB_DSI0_HS20 0x400f40a4u
#define CYREG_UDB_DSI0_HS21 0x400f40a5u
#define CYREG_UDB_DSI0_HS22 0x400f40a6u
#define CYREG_UDB_DSI0_HS23 0x400f40a7u
#define CYREG_UDB_DSI0_HV_R0 0x400f40a8u
#define CYREG_UDB_DSI0_HV_R1 0x400f40a9u
#define CYREG_UDB_DSI0_HV_R2 0x400f40aau
#define CYREG_UDB_DSI0_HV_R3 0x400f40abu
#define CYREG_UDB_DSI0_HV_R4 0x400f40acu
#define CYREG_UDB_DSI0_HV_R5 0x400f40adu
#define CYREG_UDB_DSI0_HV_R6 0x400f40aeu
#define CYREG_UDB_DSI0_HV_R7 0x400f40afu
#define CYREG_UDB_DSI0_HV_R8 0x400f40b0u
#define CYREG_UDB_DSI0_HV_R9 0x400f40b1u
#define CYREG_UDB_DSI0_HV_R10 0x400f40b2u
#define CYREG_UDB_DSI0_HV_R11 0x400f40b3u
#define CYREG_UDB_DSI0_HV_R12 0x400f40b4u
#define CYREG_UDB_DSI0_HV_R13 0x400f40b5u
#define CYREG_UDB_DSI0_HV_R14 0x400f40b6u
#define CYREG_UDB_DSI0_HV_R15 0x400f40b7u
#define CYREG_UDB_DSI0_DSIINP0 0x400f40c0u
#define CYFLD_UDB_DSI_PI_TOP__OFFSET 0x00000000u
#define CYFLD_UDB_DSI_PI_TOP__SIZE 0x00000004u
#define CYFLD_UDB_DSI_PI_BOT__OFFSET 0x00000004u
#define CYFLD_UDB_DSI_PI_BOT__SIZE 0x00000004u
#define CYREG_UDB_DSI0_DSIINP1 0x400f40c2u
#define CYREG_UDB_DSI0_DSIINP2 0x400f40c4u
#define CYREG_UDB_DSI0_DSIINP3 0x400f40c6u
#define CYREG_UDB_DSI0_DSIINP4 0x400f40c8u
#define CYREG_UDB_DSI0_DSIINP5 0x400f40cau
#define CYREG_UDB_DSI0_DSIOUTP0 0x400f40ccu
#define CYREG_UDB_DSI0_DSIOUTP1 0x400f40ceu
#define CYREG_UDB_DSI0_DSIOUTP2 0x400f40d0u
#define CYREG_UDB_DSI0_DSIOUTP3 0x400f40d2u
#define CYREG_UDB_DSI0_DSIOUTT0 0x400f40d4u
#define CYREG_UDB_DSI0_DSIOUTT1 0x400f40d6u
#define CYREG_UDB_DSI0_DSIOUTT2 0x400f40d8u
#define CYREG_UDB_DSI0_DSIOUTT3 0x400f40dau
#define CYREG_UDB_DSI0_DSIOUTT4 0x400f40dcu
#define CYREG_UDB_DSI0_DSIOUTT5 0x400f40deu
#define CYREG_UDB_DSI0_VS0 0x400f40e0u
#define CYFLD_UDB_DSI_VS_TOP__OFFSET 0x00000000u
#define CYFLD_UDB_DSI_VS_TOP__SIZE 0x00000004u
#define CYFLD_UDB_DSI_VS_BOT__OFFSET 0x00000004u
#define CYFLD_UDB_DSI_VS_BOT__SIZE 0x00000004u
#define CYREG_UDB_DSI0_VS1 0x400f40e2u
#define CYREG_UDB_DSI0_VS2 0x400f40e4u
#define CYREG_UDB_DSI0_VS3 0x400f40e6u
#define CYREG_UDB_DSI0_VS4 0x400f40e8u
#define CYREG_UDB_DSI0_VS5 0x400f40eau
#define CYREG_UDB_DSI0_VS6 0x400f40ecu
#define CYREG_UDB_DSI0_VS7 0x400f40eeu
#define CYDEV_UDB_DSI1_BASE 0x400f4100u
#define CYDEV_UDB_DSI1_SIZE 0x00000100u
#define CYREG_UDB_DSI1_HC0 0x400f4100u
#define CYREG_UDB_DSI1_HC1 0x400f4101u
#define CYREG_UDB_DSI1_HC2 0x400f4102u
#define CYREG_UDB_DSI1_HC3 0x400f4103u
#define CYREG_UDB_DSI1_HC4 0x400f4104u
#define CYREG_UDB_DSI1_HC5 0x400f4105u
#define CYREG_UDB_DSI1_HC6 0x400f4106u
#define CYREG_UDB_DSI1_HC7 0x400f4107u
#define CYREG_UDB_DSI1_HC8 0x400f4108u
#define CYREG_UDB_DSI1_HC9 0x400f4109u
#define CYREG_UDB_DSI1_HC10 0x400f410au
#define CYREG_UDB_DSI1_HC11 0x400f410bu
#define CYREG_UDB_DSI1_HC12 0x400f410cu
#define CYREG_UDB_DSI1_HC13 0x400f410du
#define CYREG_UDB_DSI1_HC14 0x400f410eu
#define CYREG_UDB_DSI1_HC15 0x400f410fu
#define CYREG_UDB_DSI1_HC16 0x400f4110u
#define CYREG_UDB_DSI1_HC17 0x400f4111u
#define CYREG_UDB_DSI1_HC18 0x400f4112u
#define CYREG_UDB_DSI1_HC19 0x400f4113u
#define CYREG_UDB_DSI1_HC20 0x400f4114u
#define CYREG_UDB_DSI1_HC21 0x400f4115u
#define CYREG_UDB_DSI1_HC22 0x400f4116u
#define CYREG_UDB_DSI1_HC23 0x400f4117u
#define CYREG_UDB_DSI1_HC24 0x400f4118u
#define CYREG_UDB_DSI1_HC25 0x400f4119u
#define CYREG_UDB_DSI1_HC26 0x400f411au
#define CYREG_UDB_DSI1_HC27 0x400f411bu
#define CYREG_UDB_DSI1_HC28 0x400f411cu
#define CYREG_UDB_DSI1_HC29 0x400f411du
#define CYREG_UDB_DSI1_HC30 0x400f411eu
#define CYREG_UDB_DSI1_HC31 0x400f411fu
#define CYREG_UDB_DSI1_HC32 0x400f4120u
#define CYREG_UDB_DSI1_HC33 0x400f4121u
#define CYREG_UDB_DSI1_HC34 0x400f4122u
#define CYREG_UDB_DSI1_HC35 0x400f4123u
#define CYREG_UDB_DSI1_HC36 0x400f4124u
#define CYREG_UDB_DSI1_HC37 0x400f4125u
#define CYREG_UDB_DSI1_HC38 0x400f4126u
#define CYREG_UDB_DSI1_HC39 0x400f4127u
#define CYREG_UDB_DSI1_HC40 0x400f4128u
#define CYREG_UDB_DSI1_HC41 0x400f4129u
#define CYREG_UDB_DSI1_HC42 0x400f412au
#define CYREG_UDB_DSI1_HC43 0x400f412bu
#define CYREG_UDB_DSI1_HC44 0x400f412cu
#define CYREG_UDB_DSI1_HC45 0x400f412du
#define CYREG_UDB_DSI1_HC46 0x400f412eu
#define CYREG_UDB_DSI1_HC47 0x400f412fu
#define CYREG_UDB_DSI1_HC48 0x400f4130u
#define CYREG_UDB_DSI1_HC49 0x400f4131u
#define CYREG_UDB_DSI1_HC50 0x400f4132u
#define CYREG_UDB_DSI1_HC51 0x400f4133u
#define CYREG_UDB_DSI1_HC52 0x400f4134u
#define CYREG_UDB_DSI1_HC53 0x400f4135u
#define CYREG_UDB_DSI1_HC54 0x400f4136u
#define CYREG_UDB_DSI1_HC55 0x400f4137u
#define CYREG_UDB_DSI1_HC56 0x400f4138u
#define CYREG_UDB_DSI1_HC57 0x400f4139u
#define CYREG_UDB_DSI1_HC58 0x400f413au
#define CYREG_UDB_DSI1_HC59 0x400f413bu
#define CYREG_UDB_DSI1_HC60 0x400f413cu
#define CYREG_UDB_DSI1_HC61 0x400f413du
#define CYREG_UDB_DSI1_HC62 0x400f413eu
#define CYREG_UDB_DSI1_HC63 0x400f413fu
#define CYREG_UDB_DSI1_HC64 0x400f4140u
#define CYREG_UDB_DSI1_HC65 0x400f4141u
#define CYREG_UDB_DSI1_HC66 0x400f4142u
#define CYREG_UDB_DSI1_HC67 0x400f4143u
#define CYREG_UDB_DSI1_HC68 0x400f4144u
#define CYREG_UDB_DSI1_HC69 0x400f4145u
#define CYREG_UDB_DSI1_HC70 0x400f4146u
#define CYREG_UDB_DSI1_HC71 0x400f4147u
#define CYREG_UDB_DSI1_HC72 0x400f4148u
#define CYREG_UDB_DSI1_HC73 0x400f4149u
#define CYREG_UDB_DSI1_HC74 0x400f414au
#define CYREG_UDB_DSI1_HC75 0x400f414bu
#define CYREG_UDB_DSI1_HC76 0x400f414cu
#define CYREG_UDB_DSI1_HC77 0x400f414du
#define CYREG_UDB_DSI1_HC78 0x400f414eu
#define CYREG_UDB_DSI1_HC79 0x400f414fu
#define CYREG_UDB_DSI1_HC80 0x400f4150u
#define CYREG_UDB_DSI1_HC81 0x400f4151u
#define CYREG_UDB_DSI1_HC82 0x400f4152u
#define CYREG_UDB_DSI1_HC83 0x400f4153u
#define CYREG_UDB_DSI1_HC84 0x400f4154u
#define CYREG_UDB_DSI1_HC85 0x400f4155u
#define CYREG_UDB_DSI1_HC86 0x400f4156u
#define CYREG_UDB_DSI1_HC87 0x400f4157u
#define CYREG_UDB_DSI1_HC88 0x400f4158u
#define CYREG_UDB_DSI1_HC89 0x400f4159u
#define CYREG_UDB_DSI1_HC90 0x400f415au
#define CYREG_UDB_DSI1_HC91 0x400f415bu
#define CYREG_UDB_DSI1_HC92 0x400f415cu
#define CYREG_UDB_DSI1_HC93 0x400f415du
#define CYREG_UDB_DSI1_HC94 0x400f415eu
#define CYREG_UDB_DSI1_HC95 0x400f415fu
#define CYREG_UDB_DSI1_HC96 0x400f4160u
#define CYREG_UDB_DSI1_HC97 0x400f4161u
#define CYREG_UDB_DSI1_HC98 0x400f4162u
#define CYREG_UDB_DSI1_HC99 0x400f4163u
#define CYREG_UDB_DSI1_HC100 0x400f4164u
#define CYREG_UDB_DSI1_HC101 0x400f4165u
#define CYREG_UDB_DSI1_HC102 0x400f4166u
#define CYREG_UDB_DSI1_HC103 0x400f4167u
#define CYREG_UDB_DSI1_HC104 0x400f4168u
#define CYREG_UDB_DSI1_HC105 0x400f4169u
#define CYREG_UDB_DSI1_HC106 0x400f416au
#define CYREG_UDB_DSI1_HC107 0x400f416bu
#define CYREG_UDB_DSI1_HC108 0x400f416cu
#define CYREG_UDB_DSI1_HC109 0x400f416du
#define CYREG_UDB_DSI1_HC110 0x400f416eu
#define CYREG_UDB_DSI1_HC111 0x400f416fu
#define CYREG_UDB_DSI1_HC112 0x400f4170u
#define CYREG_UDB_DSI1_HC113 0x400f4171u
#define CYREG_UDB_DSI1_HC114 0x400f4172u
#define CYREG_UDB_DSI1_HC115 0x400f4173u
#define CYREG_UDB_DSI1_HC116 0x400f4174u
#define CYREG_UDB_DSI1_HC117 0x400f4175u
#define CYREG_UDB_DSI1_HC118 0x400f4176u
#define CYREG_UDB_DSI1_HC119 0x400f4177u
#define CYREG_UDB_DSI1_HC120 0x400f4178u
#define CYREG_UDB_DSI1_HC121 0x400f4179u
#define CYREG_UDB_DSI1_HC122 0x400f417au
#define CYREG_UDB_DSI1_HC123 0x400f417bu
#define CYREG_UDB_DSI1_HC124 0x400f417cu
#define CYREG_UDB_DSI1_HC125 0x400f417du
#define CYREG_UDB_DSI1_HC126 0x400f417eu
#define CYREG_UDB_DSI1_HC127 0x400f417fu
#define CYREG_UDB_DSI1_HV_L0 0x400f4180u
#define CYREG_UDB_DSI1_HV_L1 0x400f4181u
#define CYREG_UDB_DSI1_HV_L2 0x400f4182u
#define CYREG_UDB_DSI1_HV_L3 0x400f4183u
#define CYREG_UDB_DSI1_HV_L4 0x400f4184u
#define CYREG_UDB_DSI1_HV_L5 0x400f4185u
#define CYREG_UDB_DSI1_HV_L6 0x400f4186u
#define CYREG_UDB_DSI1_HV_L7 0x400f4187u
#define CYREG_UDB_DSI1_HV_L8 0x400f4188u
#define CYREG_UDB_DSI1_HV_L9 0x400f4189u
#define CYREG_UDB_DSI1_HV_L10 0x400f418au
#define CYREG_UDB_DSI1_HV_L11 0x400f418bu
#define CYREG_UDB_DSI1_HV_L12 0x400f418cu
#define CYREG_UDB_DSI1_HV_L13 0x400f418du
#define CYREG_UDB_DSI1_HV_L14 0x400f418eu
#define CYREG_UDB_DSI1_HV_L15 0x400f418fu
#define CYREG_UDB_DSI1_HS0 0x400f4190u
#define CYREG_UDB_DSI1_HS1 0x400f4191u
#define CYREG_UDB_DSI1_HS2 0x400f4192u
#define CYREG_UDB_DSI1_HS3 0x400f4193u
#define CYREG_UDB_DSI1_HS4 0x400f4194u
#define CYREG_UDB_DSI1_HS5 0x400f4195u
#define CYREG_UDB_DSI1_HS6 0x400f4196u
#define CYREG_UDB_DSI1_HS7 0x400f4197u
#define CYREG_UDB_DSI1_HS8 0x400f4198u
#define CYREG_UDB_DSI1_HS9 0x400f4199u
#define CYREG_UDB_DSI1_HS10 0x400f419au
#define CYREG_UDB_DSI1_HS11 0x400f419bu
#define CYREG_UDB_DSI1_HS12 0x400f419cu
#define CYREG_UDB_DSI1_HS13 0x400f419du
#define CYREG_UDB_DSI1_HS14 0x400f419eu
#define CYREG_UDB_DSI1_HS15 0x400f419fu
#define CYREG_UDB_DSI1_HS16 0x400f41a0u
#define CYREG_UDB_DSI1_HS17 0x400f41a1u
#define CYREG_UDB_DSI1_HS18 0x400f41a2u
#define CYREG_UDB_DSI1_HS19 0x400f41a3u
#define CYREG_UDB_DSI1_HS20 0x400f41a4u
#define CYREG_UDB_DSI1_HS21 0x400f41a5u
#define CYREG_UDB_DSI1_HS22 0x400f41a6u
#define CYREG_UDB_DSI1_HS23 0x400f41a7u
#define CYREG_UDB_DSI1_HV_R0 0x400f41a8u
#define CYREG_UDB_DSI1_HV_R1 0x400f41a9u
#define CYREG_UDB_DSI1_HV_R2 0x400f41aau
#define CYREG_UDB_DSI1_HV_R3 0x400f41abu
#define CYREG_UDB_DSI1_HV_R4 0x400f41acu
#define CYREG_UDB_DSI1_HV_R5 0x400f41adu
#define CYREG_UDB_DSI1_HV_R6 0x400f41aeu
#define CYREG_UDB_DSI1_HV_R7 0x400f41afu
#define CYREG_UDB_DSI1_HV_R8 0x400f41b0u
#define CYREG_UDB_DSI1_HV_R9 0x400f41b1u
#define CYREG_UDB_DSI1_HV_R10 0x400f41b2u
#define CYREG_UDB_DSI1_HV_R11 0x400f41b3u
#define CYREG_UDB_DSI1_HV_R12 0x400f41b4u
#define CYREG_UDB_DSI1_HV_R13 0x400f41b5u
#define CYREG_UDB_DSI1_HV_R14 0x400f41b6u
#define CYREG_UDB_DSI1_HV_R15 0x400f41b7u
#define CYREG_UDB_DSI1_DSIINP0 0x400f41c0u
#define CYREG_UDB_DSI1_DSIINP1 0x400f41c2u
#define CYREG_UDB_DSI1_DSIINP2 0x400f41c4u
#define CYREG_UDB_DSI1_DSIINP3 0x400f41c6u
#define CYREG_UDB_DSI1_DSIINP4 0x400f41c8u
#define CYREG_UDB_DSI1_DSIINP5 0x400f41cau
#define CYREG_UDB_DSI1_DSIOUTP0 0x400f41ccu
#define CYREG_UDB_DSI1_DSIOUTP1 0x400f41ceu
#define CYREG_UDB_DSI1_DSIOUTP2 0x400f41d0u
#define CYREG_UDB_DSI1_DSIOUTP3 0x400f41d2u
#define CYREG_UDB_DSI1_DSIOUTT0 0x400f41d4u
#define CYREG_UDB_DSI1_DSIOUTT1 0x400f41d6u
#define CYREG_UDB_DSI1_DSIOUTT2 0x400f41d8u
#define CYREG_UDB_DSI1_DSIOUTT3 0x400f41dau
#define CYREG_UDB_DSI1_DSIOUTT4 0x400f41dcu
#define CYREG_UDB_DSI1_DSIOUTT5 0x400f41deu
#define CYREG_UDB_DSI1_VS0 0x400f41e0u
#define CYREG_UDB_DSI1_VS1 0x400f41e2u
#define CYREG_UDB_DSI1_VS2 0x400f41e4u
#define CYREG_UDB_DSI1_VS3 0x400f41e6u
#define CYREG_UDB_DSI1_VS4 0x400f41e8u
#define CYREG_UDB_DSI1_VS5 0x400f41eau
#define CYREG_UDB_DSI1_VS6 0x400f41ecu
#define CYREG_UDB_DSI1_VS7 0x400f41eeu
#define CYDEV_UDB_DSI2_BASE 0x400f4200u
#define CYDEV_UDB_DSI2_SIZE 0x00000100u
#define CYREG_UDB_DSI2_HC0 0x400f4200u
#define CYREG_UDB_DSI2_HC1 0x400f4201u
#define CYREG_UDB_DSI2_HC2 0x400f4202u
#define CYREG_UDB_DSI2_HC3 0x400f4203u
#define CYREG_UDB_DSI2_HC4 0x400f4204u
#define CYREG_UDB_DSI2_HC5 0x400f4205u
#define CYREG_UDB_DSI2_HC6 0x400f4206u
#define CYREG_UDB_DSI2_HC7 0x400f4207u
#define CYREG_UDB_DSI2_HC8 0x400f4208u
#define CYREG_UDB_DSI2_HC9 0x400f4209u
#define CYREG_UDB_DSI2_HC10 0x400f420au
#define CYREG_UDB_DSI2_HC11 0x400f420bu
#define CYREG_UDB_DSI2_HC12 0x400f420cu
#define CYREG_UDB_DSI2_HC13 0x400f420du
#define CYREG_UDB_DSI2_HC14 0x400f420eu
#define CYREG_UDB_DSI2_HC15 0x400f420fu
#define CYREG_UDB_DSI2_HC16 0x400f4210u
#define CYREG_UDB_DSI2_HC17 0x400f4211u
#define CYREG_UDB_DSI2_HC18 0x400f4212u
#define CYREG_UDB_DSI2_HC19 0x400f4213u
#define CYREG_UDB_DSI2_HC20 0x400f4214u
#define CYREG_UDB_DSI2_HC21 0x400f4215u
#define CYREG_UDB_DSI2_HC22 0x400f4216u
#define CYREG_UDB_DSI2_HC23 0x400f4217u
#define CYREG_UDB_DSI2_HC24 0x400f4218u
#define CYREG_UDB_DSI2_HC25 0x400f4219u
#define CYREG_UDB_DSI2_HC26 0x400f421au
#define CYREG_UDB_DSI2_HC27 0x400f421bu
#define CYREG_UDB_DSI2_HC28 0x400f421cu
#define CYREG_UDB_DSI2_HC29 0x400f421du
#define CYREG_UDB_DSI2_HC30 0x400f421eu
#define CYREG_UDB_DSI2_HC31 0x400f421fu
#define CYREG_UDB_DSI2_HC32 0x400f4220u
#define CYREG_UDB_DSI2_HC33 0x400f4221u
#define CYREG_UDB_DSI2_HC34 0x400f4222u
#define CYREG_UDB_DSI2_HC35 0x400f4223u
#define CYREG_UDB_DSI2_HC36 0x400f4224u
#define CYREG_UDB_DSI2_HC37 0x400f4225u
#define CYREG_UDB_DSI2_HC38 0x400f4226u
#define CYREG_UDB_DSI2_HC39 0x400f4227u
#define CYREG_UDB_DSI2_HC40 0x400f4228u
#define CYREG_UDB_DSI2_HC41 0x400f4229u
#define CYREG_UDB_DSI2_HC42 0x400f422au
#define CYREG_UDB_DSI2_HC43 0x400f422bu
#define CYREG_UDB_DSI2_HC44 0x400f422cu
#define CYREG_UDB_DSI2_HC45 0x400f422du
#define CYREG_UDB_DSI2_HC46 0x400f422eu
#define CYREG_UDB_DSI2_HC47 0x400f422fu
#define CYREG_UDB_DSI2_HC48 0x400f4230u
#define CYREG_UDB_DSI2_HC49 0x400f4231u
#define CYREG_UDB_DSI2_HC50 0x400f4232u
#define CYREG_UDB_DSI2_HC51 0x400f4233u
#define CYREG_UDB_DSI2_HC52 0x400f4234u
#define CYREG_UDB_DSI2_HC53 0x400f4235u
#define CYREG_UDB_DSI2_HC54 0x400f4236u
#define CYREG_UDB_DSI2_HC55 0x400f4237u
#define CYREG_UDB_DSI2_HC56 0x400f4238u
#define CYREG_UDB_DSI2_HC57 0x400f4239u
#define CYREG_UDB_DSI2_HC58 0x400f423au
#define CYREG_UDB_DSI2_HC59 0x400f423bu
#define CYREG_UDB_DSI2_HC60 0x400f423cu
#define CYREG_UDB_DSI2_HC61 0x400f423du
#define CYREG_UDB_DSI2_HC62 0x400f423eu
#define CYREG_UDB_DSI2_HC63 0x400f423fu
#define CYREG_UDB_DSI2_HC64 0x400f4240u
#define CYREG_UDB_DSI2_HC65 0x400f4241u
#define CYREG_UDB_DSI2_HC66 0x400f4242u
#define CYREG_UDB_DSI2_HC67 0x400f4243u
#define CYREG_UDB_DSI2_HC68 0x400f4244u
#define CYREG_UDB_DSI2_HC69 0x400f4245u
#define CYREG_UDB_DSI2_HC70 0x400f4246u
#define CYREG_UDB_DSI2_HC71 0x400f4247u
#define CYREG_UDB_DSI2_HC72 0x400f4248u
#define CYREG_UDB_DSI2_HC73 0x400f4249u
#define CYREG_UDB_DSI2_HC74 0x400f424au
#define CYREG_UDB_DSI2_HC75 0x400f424bu
#define CYREG_UDB_DSI2_HC76 0x400f424cu
#define CYREG_UDB_DSI2_HC77 0x400f424du
#define CYREG_UDB_DSI2_HC78 0x400f424eu
#define CYREG_UDB_DSI2_HC79 0x400f424fu
#define CYREG_UDB_DSI2_HC80 0x400f4250u
#define CYREG_UDB_DSI2_HC81 0x400f4251u
#define CYREG_UDB_DSI2_HC82 0x400f4252u
#define CYREG_UDB_DSI2_HC83 0x400f4253u
#define CYREG_UDB_DSI2_HC84 0x400f4254u
#define CYREG_UDB_DSI2_HC85 0x400f4255u
#define CYREG_UDB_DSI2_HC86 0x400f4256u
#define CYREG_UDB_DSI2_HC87 0x400f4257u
#define CYREG_UDB_DSI2_HC88 0x400f4258u
#define CYREG_UDB_DSI2_HC89 0x400f4259u
#define CYREG_UDB_DSI2_HC90 0x400f425au
#define CYREG_UDB_DSI2_HC91 0x400f425bu
#define CYREG_UDB_DSI2_HC92 0x400f425cu
#define CYREG_UDB_DSI2_HC93 0x400f425du
#define CYREG_UDB_DSI2_HC94 0x400f425eu
#define CYREG_UDB_DSI2_HC95 0x400f425fu
#define CYREG_UDB_DSI2_HC96 0x400f4260u
#define CYREG_UDB_DSI2_HC97 0x400f4261u
#define CYREG_UDB_DSI2_HC98 0x400f4262u
#define CYREG_UDB_DSI2_HC99 0x400f4263u
#define CYREG_UDB_DSI2_HC100 0x400f4264u
#define CYREG_UDB_DSI2_HC101 0x400f4265u
#define CYREG_UDB_DSI2_HC102 0x400f4266u
#define CYREG_UDB_DSI2_HC103 0x400f4267u
#define CYREG_UDB_DSI2_HC104 0x400f4268u
#define CYREG_UDB_DSI2_HC105 0x400f4269u
#define CYREG_UDB_DSI2_HC106 0x400f426au
#define CYREG_UDB_DSI2_HC107 0x400f426bu
#define CYREG_UDB_DSI2_HC108 0x400f426cu
#define CYREG_UDB_DSI2_HC109 0x400f426du
#define CYREG_UDB_DSI2_HC110 0x400f426eu
#define CYREG_UDB_DSI2_HC111 0x400f426fu
#define CYREG_UDB_DSI2_HC112 0x400f4270u
#define CYREG_UDB_DSI2_HC113 0x400f4271u
#define CYREG_UDB_DSI2_HC114 0x400f4272u
#define CYREG_UDB_DSI2_HC115 0x400f4273u
#define CYREG_UDB_DSI2_HC116 0x400f4274u
#define CYREG_UDB_DSI2_HC117 0x400f4275u
#define CYREG_UDB_DSI2_HC118 0x400f4276u
#define CYREG_UDB_DSI2_HC119 0x400f4277u
#define CYREG_UDB_DSI2_HC120 0x400f4278u
#define CYREG_UDB_DSI2_HC121 0x400f4279u
#define CYREG_UDB_DSI2_HC122 0x400f427au
#define CYREG_UDB_DSI2_HC123 0x400f427bu
#define CYREG_UDB_DSI2_HC124 0x400f427cu
#define CYREG_UDB_DSI2_HC125 0x400f427du
#define CYREG_UDB_DSI2_HC126 0x400f427eu
#define CYREG_UDB_DSI2_HC127 0x400f427fu
#define CYREG_UDB_DSI2_HV_L0 0x400f4280u
#define CYREG_UDB_DSI2_HV_L1 0x400f4281u
#define CYREG_UDB_DSI2_HV_L2 0x400f4282u
#define CYREG_UDB_DSI2_HV_L3 0x400f4283u
#define CYREG_UDB_DSI2_HV_L4 0x400f4284u
#define CYREG_UDB_DSI2_HV_L5 0x400f4285u
#define CYREG_UDB_DSI2_HV_L6 0x400f4286u
#define CYREG_UDB_DSI2_HV_L7 0x400f4287u
#define CYREG_UDB_DSI2_HV_L8 0x400f4288u
#define CYREG_UDB_DSI2_HV_L9 0x400f4289u
#define CYREG_UDB_DSI2_HV_L10 0x400f428au
#define CYREG_UDB_DSI2_HV_L11 0x400f428bu
#define CYREG_UDB_DSI2_HV_L12 0x400f428cu
#define CYREG_UDB_DSI2_HV_L13 0x400f428du
#define CYREG_UDB_DSI2_HV_L14 0x400f428eu
#define CYREG_UDB_DSI2_HV_L15 0x400f428fu
#define CYREG_UDB_DSI2_HS0 0x400f4290u
#define CYREG_UDB_DSI2_HS1 0x400f4291u
#define CYREG_UDB_DSI2_HS2 0x400f4292u
#define CYREG_UDB_DSI2_HS3 0x400f4293u
#define CYREG_UDB_DSI2_HS4 0x400f4294u
#define CYREG_UDB_DSI2_HS5 0x400f4295u
#define CYREG_UDB_DSI2_HS6 0x400f4296u
#define CYREG_UDB_DSI2_HS7 0x400f4297u
#define CYREG_UDB_DSI2_HS8 0x400f4298u
#define CYREG_UDB_DSI2_HS9 0x400f4299u
#define CYREG_UDB_DSI2_HS10 0x400f429au
#define CYREG_UDB_DSI2_HS11 0x400f429bu
#define CYREG_UDB_DSI2_HS12 0x400f429cu
#define CYREG_UDB_DSI2_HS13 0x400f429du
#define CYREG_UDB_DSI2_HS14 0x400f429eu
#define CYREG_UDB_DSI2_HS15 0x400f429fu
#define CYREG_UDB_DSI2_HS16 0x400f42a0u
#define CYREG_UDB_DSI2_HS17 0x400f42a1u
#define CYREG_UDB_DSI2_HS18 0x400f42a2u
#define CYREG_UDB_DSI2_HS19 0x400f42a3u
#define CYREG_UDB_DSI2_HS20 0x400f42a4u
#define CYREG_UDB_DSI2_HS21 0x400f42a5u
#define CYREG_UDB_DSI2_HS22 0x400f42a6u
#define CYREG_UDB_DSI2_HS23 0x400f42a7u
#define CYREG_UDB_DSI2_HV_R0 0x400f42a8u
#define CYREG_UDB_DSI2_HV_R1 0x400f42a9u
#define CYREG_UDB_DSI2_HV_R2 0x400f42aau
#define CYREG_UDB_DSI2_HV_R3 0x400f42abu
#define CYREG_UDB_DSI2_HV_R4 0x400f42acu
#define CYREG_UDB_DSI2_HV_R5 0x400f42adu
#define CYREG_UDB_DSI2_HV_R6 0x400f42aeu
#define CYREG_UDB_DSI2_HV_R7 0x400f42afu
#define CYREG_UDB_DSI2_HV_R8 0x400f42b0u
#define CYREG_UDB_DSI2_HV_R9 0x400f42b1u
#define CYREG_UDB_DSI2_HV_R10 0x400f42b2u
#define CYREG_UDB_DSI2_HV_R11 0x400f42b3u
#define CYREG_UDB_DSI2_HV_R12 0x400f42b4u
#define CYREG_UDB_DSI2_HV_R13 0x400f42b5u
#define CYREG_UDB_DSI2_HV_R14 0x400f42b6u
#define CYREG_UDB_DSI2_HV_R15 0x400f42b7u
#define CYREG_UDB_DSI2_DSIINP0 0x400f42c0u
#define CYREG_UDB_DSI2_DSIINP1 0x400f42c2u
#define CYREG_UDB_DSI2_DSIINP2 0x400f42c4u
#define CYREG_UDB_DSI2_DSIINP3 0x400f42c6u
#define CYREG_UDB_DSI2_DSIINP4 0x400f42c8u
#define CYREG_UDB_DSI2_DSIINP5 0x400f42cau
#define CYREG_UDB_DSI2_DSIOUTP0 0x400f42ccu
#define CYREG_UDB_DSI2_DSIOUTP1 0x400f42ceu
#define CYREG_UDB_DSI2_DSIOUTP2 0x400f42d0u
#define CYREG_UDB_DSI2_DSIOUTP3 0x400f42d2u
#define CYREG_UDB_DSI2_DSIOUTT0 0x400f42d4u
#define CYREG_UDB_DSI2_DSIOUTT1 0x400f42d6u
#define CYREG_UDB_DSI2_DSIOUTT2 0x400f42d8u
#define CYREG_UDB_DSI2_DSIOUTT3 0x400f42dau
#define CYREG_UDB_DSI2_DSIOUTT4 0x400f42dcu
#define CYREG_UDB_DSI2_DSIOUTT5 0x400f42deu
#define CYREG_UDB_DSI2_VS0 0x400f42e0u
#define CYREG_UDB_DSI2_VS1 0x400f42e2u
#define CYREG_UDB_DSI2_VS2 0x400f42e4u
#define CYREG_UDB_DSI2_VS3 0x400f42e6u
#define CYREG_UDB_DSI2_VS4 0x400f42e8u
#define CYREG_UDB_DSI2_VS5 0x400f42eau
#define CYREG_UDB_DSI2_VS6 0x400f42ecu
#define CYREG_UDB_DSI2_VS7 0x400f42eeu
#define CYDEV_UDB_DSI3_BASE 0x400f4300u
#define CYDEV_UDB_DSI3_SIZE 0x00000100u
#define CYREG_UDB_DSI3_HC0 0x400f4300u
#define CYREG_UDB_DSI3_HC1 0x400f4301u
#define CYREG_UDB_DSI3_HC2 0x400f4302u
#define CYREG_UDB_DSI3_HC3 0x400f4303u
#define CYREG_UDB_DSI3_HC4 0x400f4304u
#define CYREG_UDB_DSI3_HC5 0x400f4305u
#define CYREG_UDB_DSI3_HC6 0x400f4306u
#define CYREG_UDB_DSI3_HC7 0x400f4307u
#define CYREG_UDB_DSI3_HC8 0x400f4308u
#define CYREG_UDB_DSI3_HC9 0x400f4309u
#define CYREG_UDB_DSI3_HC10 0x400f430au
#define CYREG_UDB_DSI3_HC11 0x400f430bu
#define CYREG_UDB_DSI3_HC12 0x400f430cu
#define CYREG_UDB_DSI3_HC13 0x400f430du
#define CYREG_UDB_DSI3_HC14 0x400f430eu
#define CYREG_UDB_DSI3_HC15 0x400f430fu
#define CYREG_UDB_DSI3_HC16 0x400f4310u
#define CYREG_UDB_DSI3_HC17 0x400f4311u
#define CYREG_UDB_DSI3_HC18 0x400f4312u
#define CYREG_UDB_DSI3_HC19 0x400f4313u
#define CYREG_UDB_DSI3_HC20 0x400f4314u
#define CYREG_UDB_DSI3_HC21 0x400f4315u
#define CYREG_UDB_DSI3_HC22 0x400f4316u
#define CYREG_UDB_DSI3_HC23 0x400f4317u
#define CYREG_UDB_DSI3_HC24 0x400f4318u
#define CYREG_UDB_DSI3_HC25 0x400f4319u
#define CYREG_UDB_DSI3_HC26 0x400f431au
#define CYREG_UDB_DSI3_HC27 0x400f431bu
#define CYREG_UDB_DSI3_HC28 0x400f431cu
#define CYREG_UDB_DSI3_HC29 0x400f431du
#define CYREG_UDB_DSI3_HC30 0x400f431eu
#define CYREG_UDB_DSI3_HC31 0x400f431fu
#define CYREG_UDB_DSI3_HC32 0x400f4320u
#define CYREG_UDB_DSI3_HC33 0x400f4321u
#define CYREG_UDB_DSI3_HC34 0x400f4322u
#define CYREG_UDB_DSI3_HC35 0x400f4323u
#define CYREG_UDB_DSI3_HC36 0x400f4324u
#define CYREG_UDB_DSI3_HC37 0x400f4325u
#define CYREG_UDB_DSI3_HC38 0x400f4326u
#define CYREG_UDB_DSI3_HC39 0x400f4327u
#define CYREG_UDB_DSI3_HC40 0x400f4328u
#define CYREG_UDB_DSI3_HC41 0x400f4329u
#define CYREG_UDB_DSI3_HC42 0x400f432au
#define CYREG_UDB_DSI3_HC43 0x400f432bu
#define CYREG_UDB_DSI3_HC44 0x400f432cu
#define CYREG_UDB_DSI3_HC45 0x400f432du
#define CYREG_UDB_DSI3_HC46 0x400f432eu
#define CYREG_UDB_DSI3_HC47 0x400f432fu
#define CYREG_UDB_DSI3_HC48 0x400f4330u
#define CYREG_UDB_DSI3_HC49 0x400f4331u
#define CYREG_UDB_DSI3_HC50 0x400f4332u
#define CYREG_UDB_DSI3_HC51 0x400f4333u
#define CYREG_UDB_DSI3_HC52 0x400f4334u
#define CYREG_UDB_DSI3_HC53 0x400f4335u
#define CYREG_UDB_DSI3_HC54 0x400f4336u
#define CYREG_UDB_DSI3_HC55 0x400f4337u
#define CYREG_UDB_DSI3_HC56 0x400f4338u
#define CYREG_UDB_DSI3_HC57 0x400f4339u
#define CYREG_UDB_DSI3_HC58 0x400f433au
#define CYREG_UDB_DSI3_HC59 0x400f433bu
#define CYREG_UDB_DSI3_HC60 0x400f433cu
#define CYREG_UDB_DSI3_HC61 0x400f433du
#define CYREG_UDB_DSI3_HC62 0x400f433eu
#define CYREG_UDB_DSI3_HC63 0x400f433fu
#define CYREG_UDB_DSI3_HC64 0x400f4340u
#define CYREG_UDB_DSI3_HC65 0x400f4341u
#define CYREG_UDB_DSI3_HC66 0x400f4342u
#define CYREG_UDB_DSI3_HC67 0x400f4343u
#define CYREG_UDB_DSI3_HC68 0x400f4344u
#define CYREG_UDB_DSI3_HC69 0x400f4345u
#define CYREG_UDB_DSI3_HC70 0x400f4346u
#define CYREG_UDB_DSI3_HC71 0x400f4347u
#define CYREG_UDB_DSI3_HC72 0x400f4348u
#define CYREG_UDB_DSI3_HC73 0x400f4349u
#define CYREG_UDB_DSI3_HC74 0x400f434au
#define CYREG_UDB_DSI3_HC75 0x400f434bu
#define CYREG_UDB_DSI3_HC76 0x400f434cu
#define CYREG_UDB_DSI3_HC77 0x400f434du
#define CYREG_UDB_DSI3_HC78 0x400f434eu
#define CYREG_UDB_DSI3_HC79 0x400f434fu
#define CYREG_UDB_DSI3_HC80 0x400f4350u
#define CYREG_UDB_DSI3_HC81 0x400f4351u
#define CYREG_UDB_DSI3_HC82 0x400f4352u
#define CYREG_UDB_DSI3_HC83 0x400f4353u
#define CYREG_UDB_DSI3_HC84 0x400f4354u
#define CYREG_UDB_DSI3_HC85 0x400f4355u
#define CYREG_UDB_DSI3_HC86 0x400f4356u
#define CYREG_UDB_DSI3_HC87 0x400f4357u
#define CYREG_UDB_DSI3_HC88 0x400f4358u
#define CYREG_UDB_DSI3_HC89 0x400f4359u
#define CYREG_UDB_DSI3_HC90 0x400f435au
#define CYREG_UDB_DSI3_HC91 0x400f435bu
#define CYREG_UDB_DSI3_HC92 0x400f435cu
#define CYREG_UDB_DSI3_HC93 0x400f435du
#define CYREG_UDB_DSI3_HC94 0x400f435eu
#define CYREG_UDB_DSI3_HC95 0x400f435fu
#define CYREG_UDB_DSI3_HC96 0x400f4360u
#define CYREG_UDB_DSI3_HC97 0x400f4361u
#define CYREG_UDB_DSI3_HC98 0x400f4362u
#define CYREG_UDB_DSI3_HC99 0x400f4363u
#define CYREG_UDB_DSI3_HC100 0x400f4364u
#define CYREG_UDB_DSI3_HC101 0x400f4365u
#define CYREG_UDB_DSI3_HC102 0x400f4366u
#define CYREG_UDB_DSI3_HC103 0x400f4367u
#define CYREG_UDB_DSI3_HC104 0x400f4368u
#define CYREG_UDB_DSI3_HC105 0x400f4369u
#define CYREG_UDB_DSI3_HC106 0x400f436au
#define CYREG_UDB_DSI3_HC107 0x400f436bu
#define CYREG_UDB_DSI3_HC108 0x400f436cu
#define CYREG_UDB_DSI3_HC109 0x400f436du
#define CYREG_UDB_DSI3_HC110 0x400f436eu
#define CYREG_UDB_DSI3_HC111 0x400f436fu
#define CYREG_UDB_DSI3_HC112 0x400f4370u
#define CYREG_UDB_DSI3_HC113 0x400f4371u
#define CYREG_UDB_DSI3_HC114 0x400f4372u
#define CYREG_UDB_DSI3_HC115 0x400f4373u
#define CYREG_UDB_DSI3_HC116 0x400f4374u
#define CYREG_UDB_DSI3_HC117 0x400f4375u
#define CYREG_UDB_DSI3_HC118 0x400f4376u
#define CYREG_UDB_DSI3_HC119 0x400f4377u
#define CYREG_UDB_DSI3_HC120 0x400f4378u
#define CYREG_UDB_DSI3_HC121 0x400f4379u
#define CYREG_UDB_DSI3_HC122 0x400f437au
#define CYREG_UDB_DSI3_HC123 0x400f437bu
#define CYREG_UDB_DSI3_HC124 0x400f437cu
#define CYREG_UDB_DSI3_HC125 0x400f437du
#define CYREG_UDB_DSI3_HC126 0x400f437eu
#define CYREG_UDB_DSI3_HC127 0x400f437fu
#define CYREG_UDB_DSI3_HV_L0 0x400f4380u
#define CYREG_UDB_DSI3_HV_L1 0x400f4381u
#define CYREG_UDB_DSI3_HV_L2 0x400f4382u
#define CYREG_UDB_DSI3_HV_L3 0x400f4383u
#define CYREG_UDB_DSI3_HV_L4 0x400f4384u
#define CYREG_UDB_DSI3_HV_L5 0x400f4385u
#define CYREG_UDB_DSI3_HV_L6 0x400f4386u
#define CYREG_UDB_DSI3_HV_L7 0x400f4387u
#define CYREG_UDB_DSI3_HV_L8 0x400f4388u
#define CYREG_UDB_DSI3_HV_L9 0x400f4389u
#define CYREG_UDB_DSI3_HV_L10 0x400f438au
#define CYREG_UDB_DSI3_HV_L11 0x400f438bu
#define CYREG_UDB_DSI3_HV_L12 0x400f438cu
#define CYREG_UDB_DSI3_HV_L13 0x400f438du
#define CYREG_UDB_DSI3_HV_L14 0x400f438eu
#define CYREG_UDB_DSI3_HV_L15 0x400f438fu
#define CYREG_UDB_DSI3_HS0 0x400f4390u
#define CYREG_UDB_DSI3_HS1 0x400f4391u
#define CYREG_UDB_DSI3_HS2 0x400f4392u
#define CYREG_UDB_DSI3_HS3 0x400f4393u
#define CYREG_UDB_DSI3_HS4 0x400f4394u
#define CYREG_UDB_DSI3_HS5 0x400f4395u
#define CYREG_UDB_DSI3_HS6 0x400f4396u
#define CYREG_UDB_DSI3_HS7 0x400f4397u
#define CYREG_UDB_DSI3_HS8 0x400f4398u
#define CYREG_UDB_DSI3_HS9 0x400f4399u
#define CYREG_UDB_DSI3_HS10 0x400f439au
#define CYREG_UDB_DSI3_HS11 0x400f439bu
#define CYREG_UDB_DSI3_HS12 0x400f439cu
#define CYREG_UDB_DSI3_HS13 0x400f439du
#define CYREG_UDB_DSI3_HS14 0x400f439eu
#define CYREG_UDB_DSI3_HS15 0x400f439fu
#define CYREG_UDB_DSI3_HS16 0x400f43a0u
#define CYREG_UDB_DSI3_HS17 0x400f43a1u
#define CYREG_UDB_DSI3_HS18 0x400f43a2u
#define CYREG_UDB_DSI3_HS19 0x400f43a3u
#define CYREG_UDB_DSI3_HS20 0x400f43a4u
#define CYREG_UDB_DSI3_HS21 0x400f43a5u
#define CYREG_UDB_DSI3_HS22 0x400f43a6u
#define CYREG_UDB_DSI3_HS23 0x400f43a7u
#define CYREG_UDB_DSI3_HV_R0 0x400f43a8u
#define CYREG_UDB_DSI3_HV_R1 0x400f43a9u
#define CYREG_UDB_DSI3_HV_R2 0x400f43aau
#define CYREG_UDB_DSI3_HV_R3 0x400f43abu
#define CYREG_UDB_DSI3_HV_R4 0x400f43acu
#define CYREG_UDB_DSI3_HV_R5 0x400f43adu
#define CYREG_UDB_DSI3_HV_R6 0x400f43aeu
#define CYREG_UDB_DSI3_HV_R7 0x400f43afu
#define CYREG_UDB_DSI3_HV_R8 0x400f43b0u
#define CYREG_UDB_DSI3_HV_R9 0x400f43b1u
#define CYREG_UDB_DSI3_HV_R10 0x400f43b2u
#define CYREG_UDB_DSI3_HV_R11 0x400f43b3u
#define CYREG_UDB_DSI3_HV_R12 0x400f43b4u
#define CYREG_UDB_DSI3_HV_R13 0x400f43b5u
#define CYREG_UDB_DSI3_HV_R14 0x400f43b6u
#define CYREG_UDB_DSI3_HV_R15 0x400f43b7u
#define CYREG_UDB_DSI3_DSIINP0 0x400f43c0u
#define CYREG_UDB_DSI3_DSIINP1 0x400f43c2u
#define CYREG_UDB_DSI3_DSIINP2 0x400f43c4u
#define CYREG_UDB_DSI3_DSIINP3 0x400f43c6u
#define CYREG_UDB_DSI3_DSIINP4 0x400f43c8u
#define CYREG_UDB_DSI3_DSIINP5 0x400f43cau
#define CYREG_UDB_DSI3_DSIOUTP0 0x400f43ccu
#define CYREG_UDB_DSI3_DSIOUTP1 0x400f43ceu
#define CYREG_UDB_DSI3_DSIOUTP2 0x400f43d0u
#define CYREG_UDB_DSI3_DSIOUTP3 0x400f43d2u
#define CYREG_UDB_DSI3_DSIOUTT0 0x400f43d4u
#define CYREG_UDB_DSI3_DSIOUTT1 0x400f43d6u
#define CYREG_UDB_DSI3_DSIOUTT2 0x400f43d8u
#define CYREG_UDB_DSI3_DSIOUTT3 0x400f43dau
#define CYREG_UDB_DSI3_DSIOUTT4 0x400f43dcu
#define CYREG_UDB_DSI3_DSIOUTT5 0x400f43deu
#define CYREG_UDB_DSI3_VS0 0x400f43e0u
#define CYREG_UDB_DSI3_VS1 0x400f43e2u
#define CYREG_UDB_DSI3_VS2 0x400f43e4u
#define CYREG_UDB_DSI3_VS3 0x400f43e6u
#define CYREG_UDB_DSI3_VS4 0x400f43e8u
#define CYREG_UDB_DSI3_VS5 0x400f43eau
#define CYREG_UDB_DSI3_VS6 0x400f43ecu
#define CYREG_UDB_DSI3_VS7 0x400f43eeu
#define CYDEV_UDB_PA0_BASE 0x400f5000u
#define CYDEV_UDB_PA0_SIZE 0x00000010u
#define CYREG_UDB_PA0_CFG0 0x400f5000u
#define CYFLD_UDB_PA_CLKIN_EN_SEL__OFFSET 0x00000000u
#define CYFLD_UDB_PA_CLKIN_EN_SEL__SIZE 0x00000002u
#define CYVAL_UDB_PA_CLKIN_EN_SEL_PIN_RC 0x00000000u
#define CYVAL_UDB_PA_CLKIN_EN_SEL_DSI_RC_0 0x00000001u
#define CYVAL_UDB_PA_CLKIN_EN_SEL_DSI_RC_1 0x00000002u
#define CYVAL_UDB_PA_CLKIN_EN_SEL_DSI_RC_2 0x00000003u
#define CYFLD_UDB_PA_CLKIN_EN_MODE__OFFSET 0x00000002u
#define CYFLD_UDB_PA_CLKIN_EN_MODE__SIZE 0x00000002u
#define CYVAL_UDB_PA_CLKIN_EN_MODE_OFF 0x00000000u
#define CYVAL_UDB_PA_CLKIN_EN_MODE_ON 0x00000001u
#define CYVAL_UDB_PA_CLKIN_EN_MODE_POSEDGE 0x00000002u
#define CYVAL_UDB_PA_CLKIN_EN_MODE_LEVEL 0x00000003u
#define CYFLD_UDB_PA_CLKIN_EN_INV__OFFSET 0x00000004u
#define CYFLD_UDB_PA_CLKIN_EN_INV__SIZE 0x00000001u
#define CYVAL_UDB_PA_CLKIN_EN_INV_NOINV 0x00000000u
#define CYVAL_UDB_PA_CLKIN_EN_INV_INV 0x00000001u
#define CYFLD_UDB_PA_CLKIN_INV__OFFSET 0x00000005u
#define CYFLD_UDB_PA_CLKIN_INV__SIZE 0x00000001u
#define CYVAL_UDB_PA_CLKIN_INV_NOINV 0x00000000u
#define CYVAL_UDB_PA_CLKIN_INV_INV 0x00000001u
#define CYFLD_UDB_PA_NC__OFFSET 0x00000006u
#define CYFLD_UDB_PA_NC__SIZE 0x00000002u
#define CYREG_UDB_PA0_CFG1 0x400f5001u
#define CYFLD_UDB_PA_CLKOUT_EN_SEL__OFFSET 0x00000000u
#define CYFLD_UDB_PA_CLKOUT_EN_SEL__SIZE 0x00000002u
#define CYVAL_UDB_PA_CLKOUT_EN_SEL_PIN_RC 0x00000000u
#define CYVAL_UDB_PA_CLKOUT_EN_SEL_DSI_RC_0 0x00000001u
#define CYVAL_UDB_PA_CLKOUT_EN_SEL_DSI_RC_1 0x00000002u
#define CYVAL_UDB_PA_CLKOUT_EN_SEL_DSI_RC_2 0x00000003u
#define CYFLD_UDB_PA_CLKOUT_EN_MODE__OFFSET 0x00000002u
#define CYFLD_UDB_PA_CLKOUT_EN_MODE__SIZE 0x00000002u
#define CYVAL_UDB_PA_CLKOUT_EN_MODE_OFF 0x00000000u
#define CYVAL_UDB_PA_CLKOUT_EN_MODE_ON 0x00000001u
#define CYVAL_UDB_PA_CLKOUT_EN_MODE_POSEDGE 0x00000002u
#define CYVAL_UDB_PA_CLKOUT_EN_MODE_LEVEL 0x00000003u
#define CYFLD_UDB_PA_CLKOUT_EN_INV__OFFSET 0x00000004u
#define CYFLD_UDB_PA_CLKOUT_EN_INV__SIZE 0x00000001u
#define CYVAL_UDB_PA_CLKOUT_EN_INV_NOINV 0x00000000u
#define CYVAL_UDB_PA_CLKOUT_EN_INV_INV 0x00000001u
#define CYFLD_UDB_PA_CLKOUT_INV__OFFSET 0x00000005u
#define CYFLD_UDB_PA_CLKOUT_INV__SIZE 0x00000001u
#define CYVAL_UDB_PA_CLKOUT_INV_NOINV 0x00000000u
#define CYVAL_UDB_PA_CLKOUT_INV_INV 0x00000001u
#define CYREG_UDB_PA0_CFG2 0x400f5002u
#define CYFLD_UDB_PA_CLKIN_SEL__OFFSET 0x00000000u
#define CYFLD_UDB_PA_CLKIN_SEL__SIZE 0x00000004u
#define CYVAL_UDB_PA_CLKIN_SEL_GCLK0 0x00000000u
#define CYVAL_UDB_PA_CLKIN_SEL_GCLK1 0x00000001u
#define CYVAL_UDB_PA_CLKIN_SEL_GCLK2 0x00000002u
#define CYVAL_UDB_PA_CLKIN_SEL_GCLK3 0x00000003u
#define CYVAL_UDB_PA_CLKIN_SEL_GCLK4 0x00000004u
#define CYVAL_UDB_PA_CLKIN_SEL_GCLK5 0x00000005u
#define CYVAL_UDB_PA_CLKIN_SEL_GCLK6 0x00000006u
#define CYVAL_UDB_PA_CLKIN_SEL_GCLK7 0x00000007u
#define CYVAL_UDB_PA_CLKIN_SEL_BUS_CLK_APP 0x00000009u
#define CYVAL_UDB_PA_CLKIN_SEL_PIN_RC 0x0000000cu
#define CYVAL_UDB_PA_CLKIN_SEL_DSI_RC_0 0x0000000du
#define CYVAL_UDB_PA_CLKIN_SEL_DSI_RC_1 0x0000000eu
#define CYVAL_UDB_PA_CLKIN_SEL_DSI_RC_2 0x0000000fu
#define CYFLD_UDB_PA_CLKOUT_SEL__OFFSET 0x00000004u
#define CYFLD_UDB_PA_CLKOUT_SEL__SIZE 0x00000004u
#define CYVAL_UDB_PA_CLKOUT_SEL_GCLK0 0x00000000u
#define CYVAL_UDB_PA_CLKOUT_SEL_GCLK1 0x00000001u
#define CYVAL_UDB_PA_CLKOUT_SEL_GCLK2 0x00000002u
#define CYVAL_UDB_PA_CLKOUT_SEL_GCLK3 0x00000003u
#define CYVAL_UDB_PA_CLKOUT_SEL_GCLK4 0x00000004u
#define CYVAL_UDB_PA_CLKOUT_SEL_GCLK5 0x00000005u
#define CYVAL_UDB_PA_CLKOUT_SEL_GCLK6 0x00000006u
#define CYVAL_UDB_PA_CLKOUT_SEL_GCLK7 0x00000007u
#define CYVAL_UDB_PA_CLKOUT_SEL_BUS_CLK_APP 0x00000009u
#define CYVAL_UDB_PA_CLKOUT_SEL_PIN_RC 0x0000000cu
#define CYVAL_UDB_PA_CLKOUT_SEL_DSI_RC_0 0x0000000du
#define CYVAL_UDB_PA_CLKOUT_SEL_DSI_RC_1 0x0000000eu
#define CYVAL_UDB_PA_CLKOUT_SEL_DSI_RC_2 0x0000000fu
#define CYREG_UDB_PA0_CFG3 0x400f5003u
#define CYFLD_UDB_PA_RES_IN_SEL__OFFSET 0x00000000u
#define CYFLD_UDB_PA_RES_IN_SEL__SIZE 0x00000002u
#define CYVAL_UDB_PA_RES_IN_SEL_PIN_RC 0x00000000u
#define CYVAL_UDB_PA_RES_IN_SEL_DSI_RC_0 0x00000001u
#define CYVAL_UDB_PA_RES_IN_SEL_DSI_RC_1 0x00000002u
#define CYVAL_UDB_PA_RES_IN_SEL_DSI_RC_2 0x00000003u
#define CYFLD_UDB_PA_RES_IN_INV__OFFSET 0x00000002u
#define CYFLD_UDB_PA_RES_IN_INV__SIZE 0x00000001u
#define CYVAL_UDB_PA_RES_IN_INV_NOINV 0x00000000u
#define CYVAL_UDB_PA_RES_IN_INV_INV 0x00000001u
#define CYFLD_UDB_PA_NC0__OFFSET 0x00000003u
#define CYFLD_UDB_PA_NC0__SIZE 0x00000001u
#define CYFLD_UDB_PA_RES_OUT_SEL__OFFSET 0x00000004u
#define CYFLD_UDB_PA_RES_OUT_SEL__SIZE 0x00000002u
#define CYVAL_UDB_PA_RES_OUT_SEL_PIN_RC 0x00000000u
#define CYVAL_UDB_PA_RES_OUT_SEL_DSI_RC_0 0x00000001u
#define CYVAL_UDB_PA_RES_OUT_SEL_DSI_RC_1 0x00000002u
#define CYVAL_UDB_PA_RES_OUT_SEL_DSI_RC_2 0x00000003u
#define CYFLD_UDB_PA_RES_OUT_INV__OFFSET 0x00000006u
#define CYFLD_UDB_PA_RES_OUT_INV__SIZE 0x00000001u
#define CYVAL_UDB_PA_RES_OUT_INV_NOINV 0x00000000u
#define CYVAL_UDB_PA_RES_OUT_INV_INV 0x00000001u
#define CYFLD_UDB_PA_NC7__OFFSET 0x00000007u
#define CYFLD_UDB_PA_NC7__SIZE 0x00000001u
#define CYREG_UDB_PA0_CFG4 0x400f5004u
#define CYFLD_UDB_PA_RES_IN_EN__OFFSET 0x00000000u
#define CYFLD_UDB_PA_RES_IN_EN__SIZE 0x00000001u
#define CYVAL_UDB_PA_RES_IN_EN_DISABLE 0x00000000u
#define CYVAL_UDB_PA_RES_IN_EN_ENABLE 0x00000001u
#define CYFLD_UDB_PA_RES_OUT_EN__OFFSET 0x00000001u
#define CYFLD_UDB_PA_RES_OUT_EN__SIZE 0x00000001u
#define CYVAL_UDB_PA_RES_OUT_EN_DISABLE 0x00000000u
#define CYVAL_UDB_PA_RES_OUT_EN_ENABLE 0x00000001u
#define CYFLD_UDB_PA_RES_OE_EN__OFFSET 0x00000002u
#define CYFLD_UDB_PA_RES_OE_EN__SIZE 0x00000001u
#define CYVAL_UDB_PA_RES_OE_EN_DISABLE 0x00000000u
#define CYVAL_UDB_PA_RES_OE_EN_ENABLE 0x00000001u
#define CYFLD_UDB_PA_NC7654__OFFSET 0x00000003u
#define CYFLD_UDB_PA_NC7654__SIZE 0x00000005u
#define CYREG_UDB_PA0_CFG5 0x400f5005u
#define CYFLD_UDB_PA_PIN_SEL__OFFSET 0x00000000u
#define CYFLD_UDB_PA_PIN_SEL__SIZE 0x00000001u
#define CYVAL_UDB_PA_PIN_SEL_PIN0 0x00000000u
#define CYVAL_UDB_PA_PIN_SEL_PIN1 0x00000001u
#define CYVAL_UDB_PA_PIN_SEL_PIN2 0x00000002u
#define CYVAL_UDB_PA_PIN_SEL_PIN3 0x00000003u
#define CYVAL_UDB_PA_PIN_SEL_PIN4 0x00000004u
#define CYVAL_UDB_PA_PIN_SEL_PIN5 0x00000005u
#define CYVAL_UDB_PA_PIN_SEL_PIN6 0x00000006u
#define CYVAL_UDB_PA_PIN_SEL_PIN7 0x00000007u
#define CYREG_UDB_PA0_CFG6 0x400f5006u
#define CYFLD_UDB_PA_IN_SYNC0__OFFSET 0x00000000u
#define CYFLD_UDB_PA_IN_SYNC0__SIZE 0x00000002u
#define CYVAL_UDB_PA_IN_SYNC0_TRANSPARENT 0x00000000u
#define CYVAL_UDB_PA_IN_SYNC0_SINGLESYNC 0x00000001u
#define CYVAL_UDB_PA_IN_SYNC0_DOUBLESYNC 0x00000002u
#define CYVAL_UDB_PA_IN_SYNC0_RSVD 0x00000003u
#define CYFLD_UDB_PA_IN_SYNC1__OFFSET 0x00000002u
#define CYFLD_UDB_PA_IN_SYNC1__SIZE 0x00000002u
#define CYVAL_UDB_PA_IN_SYNC1_TRANSPARENT 0x00000000u
#define CYVAL_UDB_PA_IN_SYNC1_SINGLESYNC 0x00000001u
#define CYVAL_UDB_PA_IN_SYNC1_DOUBLESYNC 0x00000002u
#define CYVAL_UDB_PA_IN_SYNC1_RSVD 0x00000003u
#define CYFLD_UDB_PA_IN_SYNC2__OFFSET 0x00000004u
#define CYFLD_UDB_PA_IN_SYNC2__SIZE 0x00000002u
#define CYVAL_UDB_PA_IN_SYNC2_TRANSPARENT 0x00000000u
#define CYVAL_UDB_PA_IN_SYNC2_SINGLESYNC 0x00000001u
#define CYVAL_UDB_PA_IN_SYNC2_DOUBLESYNC 0x00000002u
#define CYVAL_UDB_PA_IN_SYNC2_RSVD 0x00000003u
#define CYFLD_UDB_PA_IN_SYNC3__OFFSET 0x00000006u
#define CYFLD_UDB_PA_IN_SYNC3__SIZE 0x00000002u
#define CYVAL_UDB_PA_IN_SYNC3_TRANSPARENT 0x00000000u
#define CYVAL_UDB_PA_IN_SYNC3_SINGLESYNC 0x00000001u
#define CYVAL_UDB_PA_IN_SYNC3_DOUBLESYNC 0x00000002u
#define CYVAL_UDB_PA_IN_SYNC3_RSVD 0x00000003u
#define CYREG_UDB_PA0_CFG7 0x400f5007u
#define CYFLD_UDB_PA_IN_SYNC4__OFFSET 0x00000000u
#define CYFLD_UDB_PA_IN_SYNC4__SIZE 0x00000002u
#define CYVAL_UDB_PA_IN_SYNC4_TRANSPARENT 0x00000000u
#define CYVAL_UDB_PA_IN_SYNC4_SINGLESYNC 0x00000001u
#define CYVAL_UDB_PA_IN_SYNC4_DOUBLESYNC 0x00000002u
#define CYVAL_UDB_PA_IN_SYNC4_RSVD 0x00000003u
#define CYFLD_UDB_PA_IN_SYNC5__OFFSET 0x00000002u
#define CYFLD_UDB_PA_IN_SYNC5__SIZE 0x00000002u
#define CYVAL_UDB_PA_IN_SYNC5_TRANSPARENT 0x00000000u
#define CYVAL_UDB_PA_IN_SYNC5_SINGLESYNC 0x00000001u
#define CYVAL_UDB_PA_IN_SYNC5_DOUBLESYNC 0x00000002u
#define CYVAL_UDB_PA_IN_SYNC5_RSVD 0x00000003u
#define CYFLD_UDB_PA_IN_SYNC6__OFFSET 0x00000004u
#define CYFLD_UDB_PA_IN_SYNC6__SIZE 0x00000002u
#define CYVAL_UDB_PA_IN_SYNC6_TRANSPARENT 0x00000000u
#define CYVAL_UDB_PA_IN_SYNC6_SINGLESYNC 0x00000001u
#define CYVAL_UDB_PA_IN_SYNC6_DOUBLESYNC 0x00000002u
#define CYVAL_UDB_PA_IN_SYNC6_RSVD 0x00000003u
#define CYFLD_UDB_PA_IN_SYNC7__OFFSET 0x00000006u
#define CYFLD_UDB_PA_IN_SYNC7__SIZE 0x00000002u
#define CYVAL_UDB_PA_IN_SYNC7_TRANSPARENT 0x00000000u
#define CYVAL_UDB_PA_IN_SYNC7_SINGLESYNC 0x00000001u
#define CYVAL_UDB_PA_IN_SYNC7_DOUBLESYNC 0x00000002u
#define CYVAL_UDB_PA_IN_SYNC7_RSVD 0x00000003u
#define CYREG_UDB_PA0_CFG8 0x400f5008u
#define CYFLD_UDB_PA_OUT_SYNC0__OFFSET 0x00000000u
#define CYFLD_UDB_PA_OUT_SYNC0__SIZE 0x00000002u
#define CYVAL_UDB_PA_OUT_SYNC0_TRANSPARENT 0x00000000u
#define CYVAL_UDB_PA_OUT_SYNC0_SINGLESYNC 0x00000001u
#define CYVAL_UDB_PA_OUT_SYNC0_CLOCK 0x00000002u
#define CYVAL_UDB_PA_OUT_SYNC0_CLOCKINV 0x00000003u
#define CYFLD_UDB_PA_OUT_SYNC1__OFFSET 0x00000002u
#define CYFLD_UDB_PA_OUT_SYNC1__SIZE 0x00000002u
#define CYVAL_UDB_PA_OUT_SYNC1_TRANSPARENT 0x00000000u
#define CYVAL_UDB_PA_OUT_SYNC1_SINGLESYNC 0x00000001u
#define CYVAL_UDB_PA_OUT_SYNC1_CLOCK 0x00000002u
#define CYVAL_UDB_PA_OUT_SYNC1_CLOCKINV 0x00000003u
#define CYFLD_UDB_PA_OUT_SYNC2__OFFSET 0x00000004u
#define CYFLD_UDB_PA_OUT_SYNC2__SIZE 0x00000002u
#define CYVAL_UDB_PA_OUT_SYNC2_TRANSPARENT 0x00000000u
#define CYVAL_UDB_PA_OUT_SYNC2_SINGLESYNC 0x00000001u
#define CYVAL_UDB_PA_OUT_SYNC2_CLOCK 0x00000002u
#define CYVAL_UDB_PA_OUT_SYNC2_CLOCKINV 0x00000003u
#define CYFLD_UDB_PA_OUT_SYNC3__OFFSET 0x00000006u
#define CYFLD_UDB_PA_OUT_SYNC3__SIZE 0x00000002u
#define CYVAL_UDB_PA_OUT_SYNC3_TRANSPARENT 0x00000000u
#define CYVAL_UDB_PA_OUT_SYNC3_SINGLESYNC 0x00000001u
#define CYVAL_UDB_PA_OUT_SYNC3_CLOCK 0x00000002u
#define CYVAL_UDB_PA_OUT_SYNC3_CLOCKINV 0x00000003u
#define CYREG_UDB_PA0_CFG9 0x400f5009u
#define CYFLD_UDB_PA_OUT_SYNC4__OFFSET 0x00000000u
#define CYFLD_UDB_PA_OUT_SYNC4__SIZE 0x00000002u
#define CYVAL_UDB_PA_OUT_SYNC4_TRANSPARENT 0x00000000u
#define CYVAL_UDB_PA_OUT_SYNC4_SINGLESYNC 0x00000001u
#define CYVAL_UDB_PA_OUT_SYNC4_CLOCK 0x00000002u
#define CYVAL_UDB_PA_OUT_SYNC4_CLOCKINV 0x00000003u
#define CYFLD_UDB_PA_OUT_SYNC5__OFFSET 0x00000002u
#define CYFLD_UDB_PA_OUT_SYNC5__SIZE 0x00000002u
#define CYVAL_UDB_PA_OUT_SYNC5_TRANSPARENT 0x00000000u
#define CYVAL_UDB_PA_OUT_SYNC5_SINGLESYNC 0x00000001u
#define CYVAL_UDB_PA_OUT_SYNC5_CLOCK 0x00000002u
#define CYVAL_UDB_PA_OUT_SYNC5_CLOCKINV 0x00000003u
#define CYFLD_UDB_PA_OUT_SYNC6__OFFSET 0x00000004u
#define CYFLD_UDB_PA_OUT_SYNC6__SIZE 0x00000002u
#define CYVAL_UDB_PA_OUT_SYNC6_TRANSPARENT 0x00000000u
#define CYVAL_UDB_PA_OUT_SYNC6_SINGLESYNC 0x00000001u
#define CYVAL_UDB_PA_OUT_SYNC6_CLOCK 0x00000002u
#define CYVAL_UDB_PA_OUT_SYNC6_CLOCKINV 0x00000003u
#define CYFLD_UDB_PA_OUT_SYNC7__OFFSET 0x00000006u
#define CYFLD_UDB_PA_OUT_SYNC7__SIZE 0x00000002u
#define CYVAL_UDB_PA_OUT_SYNC7_TRANSPARENT 0x00000000u
#define CYVAL_UDB_PA_OUT_SYNC7_SINGLESYNC 0x00000001u
#define CYVAL_UDB_PA_OUT_SYNC7_CLOCK 0x00000002u
#define CYVAL_UDB_PA_OUT_SYNC7_CLOCKINV 0x00000003u
#define CYREG_UDB_PA0_CFG10 0x400f500au
#define CYFLD_UDB_PA_DATA_SEL0__OFFSET 0x00000000u
#define CYFLD_UDB_PA_DATA_SEL0__SIZE 0x00000002u
#define CYVAL_UDB_PA_DATA_SEL0_DSI_OUTPUT0 0x00000000u
#define CYVAL_UDB_PA_DATA_SEL0_DSI_OUTPUT1 0x00000001u
#define CYVAL_UDB_PA_DATA_SEL0_DSI_OUTPUT2 0x00000002u
#define CYVAL_UDB_PA_DATA_SEL0_DSI_OUTPUT3 0x00000003u
#define CYFLD_UDB_PA_DATA_SEL1__OFFSET 0x00000002u
#define CYFLD_UDB_PA_DATA_SEL1__SIZE 0x00000002u
#define CYVAL_UDB_PA_DATA_SEL1_DSI_OUTPUT0 0x00000000u
#define CYVAL_UDB_PA_DATA_SEL1_DSI_OUTPUT1 0x00000001u
#define CYVAL_UDB_PA_DATA_SEL1_DSI_OUTPUT2 0x00000002u
#define CYVAL_UDB_PA_DATA_SEL1_DSI_OUTPUT3 0x00000003u
#define CYFLD_UDB_PA_DATA_SEL2__OFFSET 0x00000004u
#define CYFLD_UDB_PA_DATA_SEL2__SIZE 0x00000002u
#define CYVAL_UDB_PA_DATA_SEL2_DSI_OUTPUT0 0x00000000u
#define CYVAL_UDB_PA_DATA_SEL2_DSI_OUTPUT1 0x00000001u
#define CYVAL_UDB_PA_DATA_SEL2_DSI_OUTPUT2 0x00000002u
#define CYVAL_UDB_PA_DATA_SEL2_DSI_OUTPUT3 0x00000003u
#define CYFLD_UDB_PA_DATA_SEL3__OFFSET 0x00000006u
#define CYFLD_UDB_PA_DATA_SEL3__SIZE 0x00000002u
#define CYVAL_UDB_PA_DATA_SEL3_DSI_OUTPUT0 0x00000000u
#define CYVAL_UDB_PA_DATA_SEL3_DSI_OUTPUT1 0x00000001u
#define CYVAL_UDB_PA_DATA_SEL3_DSI_OUTPUT2 0x00000002u
#define CYVAL_UDB_PA_DATA_SEL3_DSI_OUTPUT3 0x00000003u
#define CYREG_UDB_PA0_CFG11 0x400f500bu
#define CYFLD_UDB_PA_DATA_SEL4__OFFSET 0x00000000u
#define CYFLD_UDB_PA_DATA_SEL4__SIZE 0x00000002u
#define CYVAL_UDB_PA_DATA_SEL4_DSI_OUTPUT0 0x00000000u
#define CYVAL_UDB_PA_DATA_SEL4_DSI_OUTPUT1 0x00000001u
#define CYVAL_UDB_PA_DATA_SEL4_DSI_OUTPUT2 0x00000002u
#define CYVAL_UDB_PA_DATA_SEL4_DSI_OUTPUT3 0x00000003u
#define CYFLD_UDB_PA_DATA_SEL5__OFFSET 0x00000002u
#define CYFLD_UDB_PA_DATA_SEL5__SIZE 0x00000002u
#define CYVAL_UDB_PA_DATA_SEL5_DSI_OUTPUT0 0x00000000u
#define CYVAL_UDB_PA_DATA_SEL5_DSI_OUTPUT1 0x00000001u
#define CYVAL_UDB_PA_DATA_SEL5_DSI_OUTPUT2 0x00000002u
#define CYVAL_UDB_PA_DATA_SEL5_DSI_OUTPUT3 0x00000003u
#define CYFLD_UDB_PA_DATA_SEL6__OFFSET 0x00000004u
#define CYFLD_UDB_PA_DATA_SEL6__SIZE 0x00000002u
#define CYVAL_UDB_PA_DATA_SEL6_DSI_OUTPUT0 0x00000000u
#define CYVAL_UDB_PA_DATA_SEL6_DSI_OUTPUT1 0x00000001u
#define CYVAL_UDB_PA_DATA_SEL6_DSI_OUTPUT2 0x00000002u
#define CYVAL_UDB_PA_DATA_SEL6_DSI_OUTPUT3 0x00000003u
#define CYFLD_UDB_PA_DATA_SEL7__OFFSET 0x00000006u
#define CYFLD_UDB_PA_DATA_SEL7__SIZE 0x00000002u
#define CYVAL_UDB_PA_DATA_SEL7_DSI_OUTPUT0 0x00000000u
#define CYVAL_UDB_PA_DATA_SEL7_DSI_OUTPUT1 0x00000001u
#define CYVAL_UDB_PA_DATA_SEL7_DSI_OUTPUT2 0x00000002u
#define CYVAL_UDB_PA_DATA_SEL7_DSI_OUTPUT3 0x00000003u
#define CYREG_UDB_PA0_CFG12 0x400f500cu
#define CYFLD_UDB_PA_OE_SEL0__OFFSET 0x00000000u
#define CYFLD_UDB_PA_OE_SEL0__SIZE 0x00000002u
#define CYVAL_UDB_PA_OE_SEL0_DSI_OE_OUT0 0x00000000u
#define CYVAL_UDB_PA_OE_SEL0_DSI_OE_OUT1 0x00000001u
#define CYVAL_UDB_PA_OE_SEL0_DSI_OE_OUT2 0x00000002u
#define CYVAL_UDB_PA_OE_SEL0_DSI_OE_OUT3 0x00000003u
#define CYFLD_UDB_PA_OE_SEL1__OFFSET 0x00000002u
#define CYFLD_UDB_PA_OE_SEL1__SIZE 0x00000002u
#define CYVAL_UDB_PA_OE_SEL1_DSI_OE_OUT0 0x00000000u
#define CYVAL_UDB_PA_OE_SEL1_DSI_OE_OUT1 0x00000001u
#define CYVAL_UDB_PA_OE_SEL1_DSI_OE_OUT2 0x00000002u
#define CYVAL_UDB_PA_OE_SEL1_DSI_OE_OUT3 0x00000003u
#define CYFLD_UDB_PA_OE_SEL2__OFFSET 0x00000004u
#define CYFLD_UDB_PA_OE_SEL2__SIZE 0x00000002u
#define CYVAL_UDB_PA_OE_SEL2_DSI_OE_OUT0 0x00000000u
#define CYVAL_UDB_PA_OE_SEL2_DSI_OE_OUT1 0x00000001u
#define CYVAL_UDB_PA_OE_SEL2_DSI_OE_OUT2 0x00000002u
#define CYVAL_UDB_PA_OE_SEL2_DSI_OE_OUT3 0x00000003u
#define CYFLD_UDB_PA_OE_SEL3__OFFSET 0x00000006u
#define CYFLD_UDB_PA_OE_SEL3__SIZE 0x00000002u
#define CYVAL_UDB_PA_OE_SEL3_DSI_OE_OUT0 0x00000000u
#define CYVAL_UDB_PA_OE_SEL3_DSI_OE_OUT1 0x00000001u
#define CYVAL_UDB_PA_OE_SEL3_DSI_OE_OUT2 0x00000002u
#define CYVAL_UDB_PA_OE_SEL3_DSI_OE_OUT3 0x00000003u
#define CYREG_UDB_PA0_CFG13 0x400f500du
#define CYFLD_UDB_PA_OE_SEL4__OFFSET 0x00000000u
#define CYFLD_UDB_PA_OE_SEL4__SIZE 0x00000002u
#define CYVAL_UDB_PA_OE_SEL4_DSI_OE_OUT0 0x00000000u
#define CYVAL_UDB_PA_OE_SEL4_DSI_OE_OUT1 0x00000001u
#define CYVAL_UDB_PA_OE_SEL4_DSI_OE_OUT2 0x00000002u
#define CYVAL_UDB_PA_OE_SEL4_DSI_OE_OUT3 0x00000003u
#define CYFLD_UDB_PA_OE_SEL5__OFFSET 0x00000002u
#define CYFLD_UDB_PA_OE_SEL5__SIZE 0x00000002u
#define CYVAL_UDB_PA_OE_SEL5_DSI_OE_OUT0 0x00000000u
#define CYVAL_UDB_PA_OE_SEL5_DSI_OE_OUT1 0x00000001u
#define CYVAL_UDB_PA_OE_SEL5_DSI_OE_OUT2 0x00000002u
#define CYVAL_UDB_PA_OE_SEL5_DSI_OE_OUT3 0x00000003u
#define CYFLD_UDB_PA_OE_SEL6__OFFSET 0x00000004u
#define CYFLD_UDB_PA_OE_SEL6__SIZE 0x00000002u
#define CYVAL_UDB_PA_OE_SEL6_DSI_OE_OUT0 0x00000000u
#define CYVAL_UDB_PA_OE_SEL6_DSI_OE_OUT1 0x00000001u
#define CYVAL_UDB_PA_OE_SEL6_DSI_OE_OUT2 0x00000002u
#define CYVAL_UDB_PA_OE_SEL6_DSI_OE_OUT3 0x00000003u
#define CYFLD_UDB_PA_OE_SEL7__OFFSET 0x00000006u
#define CYFLD_UDB_PA_OE_SEL7__SIZE 0x00000002u
#define CYVAL_UDB_PA_OE_SEL7_DSI_OE_OUT0 0x00000000u
#define CYVAL_UDB_PA_OE_SEL7_DSI_OE_OUT1 0x00000001u
#define CYVAL_UDB_PA_OE_SEL7_DSI_OE_OUT2 0x00000002u
#define CYVAL_UDB_PA_OE_SEL7_DSI_OE_OUT3 0x00000003u
#define CYREG_UDB_PA0_CFG14 0x400f500eu
#define CYFLD_UDB_PA_OE_SYNC0__OFFSET 0x00000000u
#define CYFLD_UDB_PA_OE_SYNC0__SIZE 0x00000002u
#define CYVAL_UDB_PA_OE_SYNC0_TRANSPARENT 0x00000000u
#define CYVAL_UDB_PA_OE_SYNC0_SINGLESYNC 0x00000001u
#define CYVAL_UDB_PA_OE_SYNC0_CONSTANT1 0x00000002u
#define CYVAL_UDB_PA_OE_SYNC0_CONSTANT0 0x00000003u
#define CYFLD_UDB_PA_OE_SYNC1__OFFSET 0x00000002u
#define CYFLD_UDB_PA_OE_SYNC1__SIZE 0x00000002u
#define CYVAL_UDB_PA_OE_SYNC1_TRANSPARENT 0x00000000u
#define CYVAL_UDB_PA_OE_SYNC1_SINGLESYNC 0x00000001u
#define CYVAL_UDB_PA_OE_SYNC1_CONSTANT1 0x00000002u
#define CYVAL_UDB_PA_OE_SYNC1_CONSTANT0 0x00000003u
#define CYFLD_UDB_PA_OE_SYNC2__OFFSET 0x00000004u
#define CYFLD_UDB_PA_OE_SYNC2__SIZE 0x00000002u
#define CYVAL_UDB_PA_OE_SYNC2_TRANSPARENT 0x00000000u
#define CYVAL_UDB_PA_OE_SYNC2_SINGLESYNC 0x00000001u
#define CYVAL_UDB_PA_OE_SYNC2_CONSTANT1 0x00000002u
#define CYVAL_UDB_PA_OE_SYNC2_CONSTANT0 0x00000003u
#define CYFLD_UDB_PA_OE_SYNC3__OFFSET 0x00000006u
#define CYFLD_UDB_PA_OE_SYNC3__SIZE 0x00000002u
#define CYVAL_UDB_PA_OE_SYNC3_TRANSPARENT 0x00000000u
#define CYVAL_UDB_PA_OE_SYNC3_SINGLESYNC 0x00000001u
#define CYVAL_UDB_PA_OE_SYNC3_CONSTANT1 0x00000002u
#define CYVAL_UDB_PA_OE_SYNC3_CONSTANT0 0x00000003u
#define CYDEV_UDB_PA1_BASE 0x400f5010u
#define CYDEV_UDB_PA1_SIZE 0x00000010u
#define CYREG_UDB_PA1_CFG0 0x400f5010u
#define CYREG_UDB_PA1_CFG1 0x400f5011u
#define CYREG_UDB_PA1_CFG2 0x400f5012u
#define CYREG_UDB_PA1_CFG3 0x400f5013u
#define CYREG_UDB_PA1_CFG4 0x400f5014u
#define CYREG_UDB_PA1_CFG5 0x400f5015u
#define CYREG_UDB_PA1_CFG6 0x400f5016u
#define CYREG_UDB_PA1_CFG7 0x400f5017u
#define CYREG_UDB_PA1_CFG8 0x400f5018u
#define CYREG_UDB_PA1_CFG9 0x400f5019u
#define CYREG_UDB_PA1_CFG10 0x400f501au
#define CYREG_UDB_PA1_CFG11 0x400f501bu
#define CYREG_UDB_PA1_CFG12 0x400f501cu
#define CYREG_UDB_PA1_CFG13 0x400f501du
#define CYREG_UDB_PA1_CFG14 0x400f501eu
#define CYDEV_UDB_PA2_BASE 0x400f5020u
#define CYDEV_UDB_PA2_SIZE 0x00000010u
#define CYREG_UDB_PA2_CFG0 0x400f5020u
#define CYREG_UDB_PA2_CFG1 0x400f5021u
#define CYREG_UDB_PA2_CFG2 0x400f5022u
#define CYREG_UDB_PA2_CFG3 0x400f5023u
#define CYREG_UDB_PA2_CFG4 0x400f5024u
#define CYREG_UDB_PA2_CFG5 0x400f5025u
#define CYREG_UDB_PA2_CFG6 0x400f5026u
#define CYREG_UDB_PA2_CFG7 0x400f5027u
#define CYREG_UDB_PA2_CFG8 0x400f5028u
#define CYREG_UDB_PA2_CFG9 0x400f5029u
#define CYREG_UDB_PA2_CFG10 0x400f502au
#define CYREG_UDB_PA2_CFG11 0x400f502bu
#define CYREG_UDB_PA2_CFG12 0x400f502cu
#define CYREG_UDB_PA2_CFG13 0x400f502du
#define CYREG_UDB_PA2_CFG14 0x400f502eu
#define CYDEV_UDB_PA3_BASE 0x400f5030u
#define CYDEV_UDB_PA3_SIZE 0x00000010u
#define CYREG_UDB_PA3_CFG0 0x400f5030u
#define CYREG_UDB_PA3_CFG1 0x400f5031u
#define CYREG_UDB_PA3_CFG2 0x400f5032u
#define CYREG_UDB_PA3_CFG3 0x400f5033u
#define CYREG_UDB_PA3_CFG4 0x400f5034u
#define CYREG_UDB_PA3_CFG5 0x400f5035u
#define CYREG_UDB_PA3_CFG6 0x400f5036u
#define CYREG_UDB_PA3_CFG7 0x400f5037u
#define CYREG_UDB_PA3_CFG8 0x400f5038u
#define CYREG_UDB_PA3_CFG9 0x400f5039u
#define CYREG_UDB_PA3_CFG10 0x400f503au
#define CYREG_UDB_PA3_CFG11 0x400f503bu
#define CYREG_UDB_PA3_CFG12 0x400f503cu
#define CYREG_UDB_PA3_CFG13 0x400f503du
#define CYREG_UDB_PA3_CFG14 0x400f503eu
#define CYDEV_UDB_BCTL0_BASE 0x400f6000u
#define CYDEV_UDB_BCTL0_SIZE 0x00001000u
#define CYREG_UDB_BCTL0_DRV 0x400f6000u
#define CYFLD_UDB_BCTL0_DRV__OFFSET 0x00000000u
#define CYFLD_UDB_BCTL0_DRV__SIZE 0x00000008u
#define CYVAL_UDB_BCTL0_DRV_DISABLE 0x00000000u
#define CYVAL_UDB_BCTL0_DRV_ENABLE 0x00000001u
#define CYREG_UDB_BCTL0_MDCLK_EN 0x400f6001u
#define CYFLD_UDB_BCTL0_DCEN__OFFSET 0x00000000u
#define CYFLD_UDB_BCTL0_DCEN__SIZE 0x00000008u
#define CYVAL_UDB_BCTL0_DCEN_DISABLE 0x00000000u
#define CYVAL_UDB_BCTL0_DCEN_ENABLE 0x00000001u
#define CYREG_UDB_BCTL0_MBCLK_EN 0x400f6002u
#define CYFLD_UDB_BCTL0_BCEN__OFFSET 0x00000000u
#define CYFLD_UDB_BCTL0_BCEN__SIZE 0x00000001u
#define CYVAL_UDB_BCTL0_BCEN_DISABLE 0x00000000u
#define CYVAL_UDB_BCTL0_BCEN_ENABLE 0x00000001u
#define CYREG_UDB_BCTL0_BOTSEL_L 0x400f6008u
#define CYFLD_UDB_BCTL0_CLK_SEL0__OFFSET 0x00000000u
#define CYFLD_UDB_BCTL0_CLK_SEL0__SIZE 0x00000002u
#define CYVAL_UDB_BCTL0_CLK_SEL0_EDGE_ENABLES 0x00000000u
#define CYVAL_UDB_BCTL0_CLK_SEL0_PORT_INPUT 0x00000001u
#define CYVAL_UDB_BCTL0_CLK_SEL0_DSI_OUTPUT 0x00000002u
#define CYVAL_UDB_BCTL0_CLK_SEL0_SYNC_DSI_OUTPUT 0x00000003u
#define CYFLD_UDB_BCTL0_CLK_SEL1__OFFSET 0x00000002u
#define CYFLD_UDB_BCTL0_CLK_SEL1__SIZE 0x00000002u
#define CYVAL_UDB_BCTL0_CLK_SEL1_EDGE_ENABLES 0x00000000u
#define CYVAL_UDB_BCTL0_CLK_SEL1_PORT_INPUT 0x00000001u
#define CYVAL_UDB_BCTL0_CLK_SEL1_DSI_OUTPUT 0x00000002u
#define CYVAL_UDB_BCTL0_CLK_SEL1_SYNC_DSI_OUTPUT 0x00000003u
#define CYFLD_UDB_BCTL0_CLK_SEL2__OFFSET 0x00000004u
#define CYFLD_UDB_BCTL0_CLK_SEL2__SIZE 0x00000002u
#define CYVAL_UDB_BCTL0_CLK_SEL2_EDGE_ENABLES 0x00000000u
#define CYVAL_UDB_BCTL0_CLK_SEL2_PORT_INPUT 0x00000001u
#define CYVAL_UDB_BCTL0_CLK_SEL2_DSI_OUTPUT 0x00000002u
#define CYVAL_UDB_BCTL0_CLK_SEL2_SYNC_DSI_OUTPUT 0x00000003u
#define CYFLD_UDB_BCTL0_CLK_SEL3__OFFSET 0x00000006u
#define CYFLD_UDB_BCTL0_CLK_SEL3__SIZE 0x00000002u
#define CYVAL_UDB_BCTL0_CLK_SEL3_EDGE_ENABLES 0x00000000u
#define CYVAL_UDB_BCTL0_CLK_SEL3_PORT_INPUT 0x00000001u
#define CYVAL_UDB_BCTL0_CLK_SEL3_DSI_OUTPUT 0x00000002u
#define CYVAL_UDB_BCTL0_CLK_SEL3_SYNC_DSI_OUTPUT 0x00000003u
#define CYREG_UDB_BCTL0_BOTSEL_U 0x400f6009u
#define CYFLD_UDB_BCTL0_CLK_SEL4__OFFSET 0x00000000u
#define CYFLD_UDB_BCTL0_CLK_SEL4__SIZE 0x00000002u
#define CYVAL_UDB_BCTL0_CLK_SEL4_EDGE_ENABLES 0x00000000u
#define CYVAL_UDB_BCTL0_CLK_SEL4_PORT_INPUT 0x00000001u
#define CYVAL_UDB_BCTL0_CLK_SEL4_DSI_OUTPUT 0x00000002u
#define CYVAL_UDB_BCTL0_CLK_SEL4_SYNC_DSI_OUTPUT 0x00000003u
#define CYFLD_UDB_BCTL0_CLK_SEL5__OFFSET 0x00000002u
#define CYFLD_UDB_BCTL0_CLK_SEL5__SIZE 0x00000002u
#define CYVAL_UDB_BCTL0_CLK_SEL5_EDGE_ENABLES 0x00000000u
#define CYVAL_UDB_BCTL0_CLK_SEL5_PORT_INPUT 0x00000001u
#define CYVAL_UDB_BCTL0_CLK_SEL5_DSI_OUTPUT 0x00000002u
#define CYVAL_UDB_BCTL0_CLK_SEL5_SYNC_DSI_OUTPUT 0x00000003u
#define CYFLD_UDB_BCTL0_CLK_SEL6__OFFSET 0x00000004u
#define CYFLD_UDB_BCTL0_CLK_SEL6__SIZE 0x00000002u
#define CYVAL_UDB_BCTL0_CLK_SEL6_EDGE_ENABLES 0x00000000u
#define CYVAL_UDB_BCTL0_CLK_SEL6_PORT_INPUT 0x00000001u
#define CYVAL_UDB_BCTL0_CLK_SEL6_DSI_OUTPUT 0x00000002u
#define CYVAL_UDB_BCTL0_CLK_SEL6_SYNC_DSI_OUTPUT 0x00000003u
#define CYFLD_UDB_BCTL0_CLK_SEL7__OFFSET 0x00000006u
#define CYFLD_UDB_BCTL0_CLK_SEL7__SIZE 0x00000002u
#define CYVAL_UDB_BCTL0_CLK_SEL7_EDGE_ENABLES 0x00000000u
#define CYVAL_UDB_BCTL0_CLK_SEL7_PORT_INPUT 0x00000001u
#define CYVAL_UDB_BCTL0_CLK_SEL7_DSI_OUTPUT 0x00000002u
#define CYVAL_UDB_BCTL0_CLK_SEL7_SYNC_DSI_OUTPUT 0x00000003u
#define CYREG_UDB_BCTL0_TOPSEL_L 0x400f600au
#define CYREG_UDB_BCTL0_TOPSEL_U 0x400f600bu
#define CYREG_UDB_BCTL0_QCLK_EN0 0x400f6010u
#define CYFLD_UDB_BCTL0_DCEN_Q__OFFSET 0x00000000u
#define CYFLD_UDB_BCTL0_DCEN_Q__SIZE 0x00000008u
#define CYVAL_UDB_BCTL0_DCEN_Q_DISABLE 0x00000000u
#define CYVAL_UDB_BCTL0_DCEN_Q_ENABLE 0x00000001u
#define CYFLD_UDB_BCTL0_BCEN_Q__OFFSET 0x00000008u
#define CYFLD_UDB_BCTL0_BCEN_Q__SIZE 0x00000001u
#define CYVAL_UDB_BCTL0_BCEN_Q_DISABLE 0x00000000u
#define CYVAL_UDB_BCTL0_BCEN_Q_ENABLE 0x00000001u
#define CYFLD_UDB_BCTL0_GCH_WR_LO__OFFSET 0x00000009u
#define CYFLD_UDB_BCTL0_GCH_WR_LO__SIZE 0x00000001u
#define CYVAL_UDB_BCTL0_GCH_WR_LO_DISABLE 0x00000000u
#define CYVAL_UDB_BCTL0_GCH_WR_LO_ENABLE 0x00000001u
#define CYFLD_UDB_BCTL0_GCH_WR_HI__OFFSET 0x0000000au
#define CYFLD_UDB_BCTL0_GCH_WR_HI__SIZE 0x00000001u
#define CYVAL_UDB_BCTL0_GCH_WR_HI_DISABLE 0x00000000u
#define CYVAL_UDB_BCTL0_GCH_WR_HI_ENABLE 0x00000001u
#define CYFLD_UDB_BCTL0_DISABLE_ROUTE__OFFSET 0x0000000bu
#define CYFLD_UDB_BCTL0_DISABLE_ROUTE__SIZE 0x00000001u
#define CYVAL_UDB_BCTL0_DISABLE_ROUTE_DISABLE 0x00000000u
#define CYVAL_UDB_BCTL0_DISABLE_ROUTE_ENABLE 0x00000001u
#define CYFLD_UDB_BCTL0_GLB_DSI_WR__OFFSET 0x0000000cu
#define CYFLD_UDB_BCTL0_GLB_DSI_WR__SIZE 0x00000001u
#define CYVAL_UDB_BCTL0_GLB_DSI_WR_DISABLE 0x00000000u
#define CYVAL_UDB_BCTL0_GLB_DSI_WR_ENABLE 0x00000001u
#define CYFLD_UDB_BCTL0_WR_CFG_OPT__OFFSET 0x0000000du
#define CYFLD_UDB_BCTL0_WR_CFG_OPT__SIZE 0x00000001u
#define CYVAL_UDB_BCTL0_WR_CFG_OPT_FULL_CYCLE_STB 0x00000000u
#define CYVAL_UDB_BCTL0_WR_CFG_OPT_HALF_CYCLE_STB 0x00000001u
#define CYFLD_UDB_BCTL0_NC0__OFFSET 0x0000000eu
#define CYFLD_UDB_BCTL0_NC0__SIZE 0x00000001u
#define CYFLD_UDB_BCTL0_SLEEP_TEST__OFFSET 0x0000000fu
#define CYFLD_UDB_BCTL0_SLEEP_TEST__SIZE 0x00000001u
#define CYVAL_UDB_BCTL0_SLEEP_TEST_DISABLE 0x00000000u
#define CYVAL_UDB_BCTL0_SLEEP_TEST_ENABLE 0x00000001u
#define CYREG_UDB_BCTL0_QCLK_EN1 0x400f6012u
#define CYDEV_UDB_UDBIF_BASE 0x400f7000u
#define CYDEV_UDB_UDBIF_SIZE 0x00001000u
#define CYREG_UDB_UDBIF_BANK_CTL 0x400f7000u
#define CYFLD_UDB_UDBIF_DIS_COR__OFFSET 0x00000000u
#define CYFLD_UDB_UDBIF_DIS_COR__SIZE 0x00000001u
#define CYVAL_UDB_UDBIF_DIS_COR_NORMAL 0x00000000u
#define CYVAL_UDB_UDBIF_DIS_COR_DISABLE 0x00000001u
#define CYFLD_UDB_UDBIF_ROUTE_EN__OFFSET 0x00000001u
#define CYFLD_UDB_UDBIF_ROUTE_EN__SIZE 0x00000001u
#define CYVAL_UDB_UDBIF_ROUTE_EN_DISABLE 0x00000000u
#define CYVAL_UDB_UDBIF_ROUTE_EN_ENABLE 0x00000001u
#define CYFLD_UDB_UDBIF_BANK_EN__OFFSET 0x00000002u
#define CYFLD_UDB_UDBIF_BANK_EN__SIZE 0x00000001u
#define CYVAL_UDB_UDBIF_BANK_EN_DISABLE 0x00000000u
#define CYVAL_UDB_UDBIF_BANK_EN_ENABLE 0x00000001u
#define CYFLD_UDB_UDBIF_LOCK__OFFSET 0x00000003u
#define CYFLD_UDB_UDBIF_LOCK__SIZE 0x00000001u
#define CYVAL_UDB_UDBIF_LOCK_MUTABLE 0x00000000u
#define CYVAL_UDB_UDBIF_LOCK_LOCKED 0x00000001u
#define CYFLD_UDB_UDBIF_PIPE__OFFSET 0x00000004u
#define CYFLD_UDB_UDBIF_PIPE__SIZE 0x00000001u
#define CYVAL_UDB_UDBIF_PIPE_BYPASS 0x00000000u
#define CYVAL_UDB_UDBIF_PIPE_PIPELINED 0x00000001u
#define CYFLD_UDB_UDBIF_GLBL_WR__OFFSET 0x00000007u
#define CYFLD_UDB_UDBIF_GLBL_WR__SIZE 0x00000001u
#define CYVAL_UDB_UDBIF_GLBL_WR_DISABLE 0x00000000u
#define CYVAL_UDB_UDBIF_GLBL_WR_ENABLE 0x00000001u
#define CYREG_UDB_UDBIF_WAIT_CFG 0x400f7001u
#define CYFLD_UDB_UDBIF_RD_CFG_WAIT__OFFSET 0x00000000u
#define CYFLD_UDB_UDBIF_RD_CFG_WAIT__SIZE 0x00000002u
#define CYVAL_UDB_UDBIF_RD_CFG_WAIT_FIVE_WAITS 0x00000000u
#define CYVAL_UDB_UDBIF_RD_CFG_WAIT_FOUR_WAITS 0x00000001u
#define CYVAL_UDB_UDBIF_RD_CFG_WAIT_THREE_WAITS 0x00000002u
#define CYVAL_UDB_UDBIF_RD_CFG_WAIT_ONE_WAIT 0x00000003u
#define CYFLD_UDB_UDBIF_WR_CFG_WAIT__OFFSET 0x00000002u
#define CYFLD_UDB_UDBIF_WR_CFG_WAIT__SIZE 0x00000002u
#define CYVAL_UDB_UDBIF_WR_CFG_WAIT_ONE_WAIT 0x00000000u
#define CYVAL_UDB_UDBIF_WR_CFG_WAIT_TWO_WAITS 0x00000001u
#define CYVAL_UDB_UDBIF_WR_CFG_WAIT_THREE_WAITS 0x00000002u
#define CYVAL_UDB_UDBIF_WR_CFG_WAIT_ZERO_WAITS 0x00000003u
#define CYFLD_UDB_UDBIF_RD_WRK_WAIT__OFFSET 0x00000004u
#define CYFLD_UDB_UDBIF_RD_WRK_WAIT__SIZE 0x00000002u
#define CYVAL_UDB_UDBIF_RD_WRK_WAIT_ONE_WAIT 0x00000000u
#define CYVAL_UDB_UDBIF_RD_WRK_WAIT_TWO_WAITS 0x00000001u
#define CYVAL_UDB_UDBIF_RD_WRK_WAIT_THREE_WAITS 0x00000002u
#define CYVAL_UDB_UDBIF_RD_WRK_WAIT_ZERO_WAITS 0x00000003u
#define CYFLD_UDB_UDBIF_WR_WRK_WAIT__OFFSET 0x00000006u
#define CYFLD_UDB_UDBIF_WR_WRK_WAIT__SIZE 0x00000002u
#define CYVAL_UDB_UDBIF_WR_WRK_WAIT_ONE_WAIT 0x00000000u
#define CYVAL_UDB_UDBIF_WR_WRK_WAIT_TWO_WAITS 0x00000001u
#define CYVAL_UDB_UDBIF_WR_WRK_WAIT_THREE_WAITS 0x00000002u
#define CYVAL_UDB_UDBIF_WR_WRK_WAIT_ZERO_WAITS 0x00000003u
#define CYREG_UDB_UDBIF_INT_CLK_CTL 0x400f701cu
#define CYFLD_UDB_UDBIF_EN_HFCLK__OFFSET 0x00000000u
#define CYFLD_UDB_UDBIF_EN_HFCLK__SIZE 0x00000001u
#define CYREG_UDB_INT_CFG 0x400f8000u
#define CYFLD_UDB_INT_MODE_CFG__OFFSET 0x00000000u
#define CYFLD_UDB_INT_MODE_CFG__SIZE 0x00000020u
#define CYVAL_UDB_INT_MODE_CFG_LEVEL 0x00000000u
#define CYVAL_UDB_INT_MODE_CFG_PULSE 0x00000001u
#define CYDEV_CTBM_BASE 0x40100000u
#define CYDEV_CTBM_SIZE 0x00010000u
#define CYREG_CTBM_CTB_CTRL 0x40100000u
#define CYFLD_CTBM_ENABLED__OFFSET 0x0000001fu
#define CYFLD_CTBM_ENABLED__SIZE 0x00000001u
#define CYREG_CTBM_OA_RES0_CTRL 0x40100004u
#define CYFLD_CTBM_OA0_PWR_MODE__OFFSET 0x00000000u
#define CYFLD_CTBM_OA0_PWR_MODE__SIZE 0x00000002u
#define CYFLD_CTBM_OA0_DRIVE_STR_SEL__OFFSET 0x00000002u
#define CYFLD_CTBM_OA0_DRIVE_STR_SEL__SIZE 0x00000001u
#define CYFLD_CTBM_OA0_COMP_EN__OFFSET 0x00000004u
#define CYFLD_CTBM_OA0_COMP_EN__SIZE 0x00000001u
#define CYFLD_CTBM_OA0_HYST_EN__OFFSET 0x00000005u
#define CYFLD_CTBM_OA0_HYST_EN__SIZE 0x00000001u
#define CYFLD_CTBM_OA0_BYPASS_DSI_SYNC__OFFSET 0x00000006u
#define CYFLD_CTBM_OA0_BYPASS_DSI_SYNC__SIZE 0x00000001u
#define CYFLD_CTBM_OA0_COMPINT__OFFSET 0x00000008u
#define CYFLD_CTBM_OA0_COMPINT__SIZE 0x00000002u
#define CYVAL_CTBM_OA0_COMPINT_DISABLE 0x00000000u
#define CYVAL_CTBM_OA0_COMPINT_RISING 0x00000001u
#define CYVAL_CTBM_OA0_COMPINT_FALLING 0x00000002u
#define CYVAL_CTBM_OA0_COMPINT_BOTH 0x00000003u
#define CYFLD_CTBM_OA0_PUMP_EN__OFFSET 0x0000000bu
#define CYFLD_CTBM_OA0_PUMP_EN__SIZE 0x00000001u
#define CYREG_CTBM_OA_RES1_CTRL 0x40100008u
#define CYFLD_CTBM_OA1_PWR_MODE__OFFSET 0x00000000u
#define CYFLD_CTBM_OA1_PWR_MODE__SIZE 0x00000002u
#define CYFLD_CTBM_OA1_DRIVE_STR_SEL__OFFSET 0x00000002u
#define CYFLD_CTBM_OA1_DRIVE_STR_SEL__SIZE 0x00000001u
#define CYFLD_CTBM_OA1_COMP_EN__OFFSET 0x00000004u
#define CYFLD_CTBM_OA1_COMP_EN__SIZE 0x00000001u
#define CYFLD_CTBM_OA1_HYST_EN__OFFSET 0x00000005u
#define CYFLD_CTBM_OA1_HYST_EN__SIZE 0x00000001u
#define CYFLD_CTBM_OA1_BYPASS_DSI_SYNC__OFFSET 0x00000006u
#define CYFLD_CTBM_OA1_BYPASS_DSI_SYNC__SIZE 0x00000001u
#define CYFLD_CTBM_OA1_COMPINT__OFFSET 0x00000008u
#define CYFLD_CTBM_OA1_COMPINT__SIZE 0x00000002u
#define CYVAL_CTBM_OA1_COMPINT_DISABLE 0x00000000u
#define CYVAL_CTBM_OA1_COMPINT_RISING 0x00000001u
#define CYVAL_CTBM_OA1_COMPINT_FALLING 0x00000002u
#define CYVAL_CTBM_OA1_COMPINT_BOTH 0x00000003u
#define CYFLD_CTBM_OA1_PUMP_EN__OFFSET 0x0000000bu
#define CYFLD_CTBM_OA1_PUMP_EN__SIZE 0x00000001u
#define CYREG_CTBM_COMP_STAT 0x4010000cu
#define CYFLD_CTBM_OA0_COMP__OFFSET 0x00000000u
#define CYFLD_CTBM_OA0_COMP__SIZE 0x00000001u
#define CYFLD_CTBM_OA1_COMP__OFFSET 0x00000010u
#define CYFLD_CTBM_OA1_COMP__SIZE 0x00000001u
#define CYREG_CTBM_INTR 0x40100020u
#define CYFLD_CTBM_COMP0__OFFSET 0x00000000u
#define CYFLD_CTBM_COMP0__SIZE 0x00000001u
#define CYFLD_CTBM_COMP1__OFFSET 0x00000001u
#define CYFLD_CTBM_COMP1__SIZE 0x00000001u
#define CYREG_CTBM_INTR_SET 0x40100024u
#define CYFLD_CTBM_COMP0_SET__OFFSET 0x00000000u
#define CYFLD_CTBM_COMP0_SET__SIZE 0x00000001u
#define CYFLD_CTBM_COMP1_SET__OFFSET 0x00000001u
#define CYFLD_CTBM_COMP1_SET__SIZE 0x00000001u
#define CYREG_CTBM_INTR_MASK 0x40100028u
#define CYFLD_CTBM_COMP0_MASK__OFFSET 0x00000000u
#define CYFLD_CTBM_COMP0_MASK__SIZE 0x00000001u
#define CYFLD_CTBM_COMP1_MASK__OFFSET 0x00000001u
#define CYFLD_CTBM_COMP1_MASK__SIZE 0x00000001u
#define CYREG_CTBM_INTR_MASKED 0x4010002cu
#define CYFLD_CTBM_COMP0_MASKED__OFFSET 0x00000000u
#define CYFLD_CTBM_COMP0_MASKED__SIZE 0x00000001u
#define CYFLD_CTBM_COMP1_MASKED__OFFSET 0x00000001u
#define CYFLD_CTBM_COMP1_MASKED__SIZE 0x00000001u
#define CYREG_CTBM_DFT_CTRL 0x40100030u
#define CYFLD_CTBM_DFT_MODE__OFFSET 0x00000000u
#define CYFLD_CTBM_DFT_MODE__SIZE 0x00000003u
#define CYFLD_CTBM_DFT_EN__OFFSET 0x0000001fu
#define CYFLD_CTBM_DFT_EN__SIZE 0x00000001u
#define CYREG_CTBM_OA0_SW 0x40100080u
#define CYFLD_CTBM_OA0P_A00__OFFSET 0x00000000u
#define CYFLD_CTBM_OA0P_A00__SIZE 0x00000001u
#define CYFLD_CTBM_OA0P_A20__OFFSET 0x00000002u
#define CYFLD_CTBM_OA0P_A20__SIZE 0x00000001u
#define CYFLD_CTBM_OA0P_A30__OFFSET 0x00000003u
#define CYFLD_CTBM_OA0P_A30__SIZE 0x00000001u
#define CYFLD_CTBM_OA0M_A11__OFFSET 0x00000008u
#define CYFLD_CTBM_OA0M_A11__SIZE 0x00000001u
#define CYFLD_CTBM_OA0M_A81__OFFSET 0x0000000eu
#define CYFLD_CTBM_OA0M_A81__SIZE 0x00000001u
#define CYFLD_CTBM_OA0O_D51__OFFSET 0x00000012u
#define CYFLD_CTBM_OA0O_D51__SIZE 0x00000001u
#define CYFLD_CTBM_OA0O_D81__OFFSET 0x00000015u
#define CYFLD_CTBM_OA0O_D81__SIZE 0x00000001u
#define CYREG_CTBM_OA0_SW_CLEAR 0x40100084u
#define CYREG_CTBM_OA1_SW 0x40100088u
#define CYFLD_CTBM_OA1P_A03__OFFSET 0x00000000u
#define CYFLD_CTBM_OA1P_A03__SIZE 0x00000001u
#define CYFLD_CTBM_OA1P_A13__OFFSET 0x00000001u
#define CYFLD_CTBM_OA1P_A13__SIZE 0x00000001u
#define CYFLD_CTBM_OA1P_A43__OFFSET 0x00000004u
#define CYFLD_CTBM_OA1P_A43__SIZE 0x00000001u
#define CYFLD_CTBM_OA1M_A22__OFFSET 0x00000008u
#define CYFLD_CTBM_OA1M_A22__SIZE 0x00000001u
#define CYFLD_CTBM_OA1M_A82__OFFSET 0x0000000eu
#define CYFLD_CTBM_OA1M_A82__SIZE 0x00000001u
#define CYFLD_CTBM_OA1O_D52__OFFSET 0x00000012u
#define CYFLD_CTBM_OA1O_D52__SIZE 0x00000001u
#define CYFLD_CTBM_OA1O_D62__OFFSET 0x00000013u
#define CYFLD_CTBM_OA1O_D62__SIZE 0x00000001u
#define CYFLD_CTBM_OA1O_D82__OFFSET 0x00000015u
#define CYFLD_CTBM_OA1O_D82__SIZE 0x00000001u
#define CYREG_CTBM_OA1_SW_CLEAR 0x4010008cu
#define CYREG_CTBM_CTB_SW_HW_CTRL 0x401000c0u
#define CYFLD_CTBM_P2_HW_CTRL__OFFSET 0x00000002u
#define CYFLD_CTBM_P2_HW_CTRL__SIZE 0x00000001u
#define CYFLD_CTBM_P3_HW_CTRL__OFFSET 0x00000003u
#define CYFLD_CTBM_P3_HW_CTRL__SIZE 0x00000001u
#define CYREG_CTBM_CTB_SW_STATUS 0x401000c4u
#define CYFLD_CTBM_OA0O_D51_STAT__OFFSET 0x0000001cu
#define CYFLD_CTBM_OA0O_D51_STAT__SIZE 0x00000001u
#define CYFLD_CTBM_OA1O_D52_STAT__OFFSET 0x0000001du
#define CYFLD_CTBM_OA1O_D52_STAT__SIZE 0x00000001u
#define CYFLD_CTBM_OA1O_D62_STAT__OFFSET 0x0000001eu
#define CYFLD_CTBM_OA1O_D62_STAT__SIZE 0x00000001u
#define CYREG_CTBM_OA0_OFFSET_TRIM 0x40100f00u
#define CYFLD_CTBM_OA0_OFFSET_TRIM__OFFSET 0x00000000u
#define CYFLD_CTBM_OA0_OFFSET_TRIM__SIZE 0x00000006u
#define CYREG_CTBM_OA0_SLOPE_OFFSET_TRIM 0x40100f04u
#define CYFLD_CTBM_OA0_SLOPE_OFFSET_TRIM__OFFSET 0x00000000u
#define CYFLD_CTBM_OA0_SLOPE_OFFSET_TRIM__SIZE 0x00000006u
#define CYREG_CTBM_OA0_COMP_TRIM 0x40100f08u
#define CYFLD_CTBM_OA0_COMP_TRIM__OFFSET 0x00000000u
#define CYFLD_CTBM_OA0_COMP_TRIM__SIZE 0x00000002u
#define CYREG_CTBM_OA1_OFFSET_TRIM 0x40100f0cu
#define CYFLD_CTBM_OA1_OFFSET_TRIM__OFFSET 0x00000000u
#define CYFLD_CTBM_OA1_OFFSET_TRIM__SIZE 0x00000006u
#define CYREG_CTBM_OA1_SLOPE_OFFSET_TRIM 0x40100f10u
#define CYFLD_CTBM_OA1_SLOPE_OFFSET_TRIM__OFFSET 0x00000000u
#define CYFLD_CTBM_OA1_SLOPE_OFFSET_TRIM__SIZE 0x00000006u
#define CYREG_CTBM_OA1_COMP_TRIM 0x40100f14u
#define CYFLD_CTBM_OA1_COMP_TRIM__OFFSET 0x00000000u
#define CYFLD_CTBM_OA1_COMP_TRIM__SIZE 0x00000002u
#define CYDEV_SAR_BASE 0x401a0000u
#define CYDEV_SAR_SIZE 0x00010000u
#define CYREG_SAR_CTRL 0x401a0000u
#define CYFLD_SAR_VREF_SEL__OFFSET 0x00000004u
#define CYFLD_SAR_VREF_SEL__SIZE 0x00000003u
#define CYVAL_SAR_VREF_SEL_VREF0 0x00000000u
#define CYVAL_SAR_VREF_SEL_VREF1 0x00000001u
#define CYVAL_SAR_VREF_SEL_VREF2 0x00000002u
#define CYVAL_SAR_VREF_SEL_VREF_AROUTE 0x00000003u
#define CYVAL_SAR_VREF_SEL_VBGR 0x00000004u
#define CYVAL_SAR_VREF_SEL_VREF_EXT 0x00000005u
#define CYVAL_SAR_VREF_SEL_VDDA_DIV_2 0x00000006u
#define CYVAL_SAR_VREF_SEL_VDDA 0x00000007u
#define CYFLD_SAR_VREF_BYP_CAP_EN__OFFSET 0x00000007u
#define CYFLD_SAR_VREF_BYP_CAP_EN__SIZE 0x00000001u
#define CYFLD_SAR_NEG_SEL__OFFSET 0x00000009u
#define CYFLD_SAR_NEG_SEL__SIZE 0x00000003u
#define CYVAL_SAR_NEG_SEL_VSSA_KELVIN 0x00000000u
#define CYVAL_SAR_NEG_SEL_ART_VSSA 0x00000001u
#define CYVAL_SAR_NEG_SEL_P1 0x00000002u
#define CYVAL_SAR_NEG_SEL_P3 0x00000003u
#define CYVAL_SAR_NEG_SEL_P5 0x00000004u
#define CYVAL_SAR_NEG_SEL_P7 0x00000005u
#define CYVAL_SAR_NEG_SEL_ACORE 0x00000006u
#define CYVAL_SAR_NEG_SEL_VREF 0x00000007u
#define CYFLD_SAR_SAR_HW_CTRL_NEGVREF__OFFSET 0x0000000du
#define CYFLD_SAR_SAR_HW_CTRL_NEGVREF__SIZE 0x00000001u
#define CYFLD_SAR_PWR_CTRL_VREF__OFFSET 0x0000000eu
#define CYFLD_SAR_PWR_CTRL_VREF__SIZE 0x00000002u
#define CYVAL_SAR_PWR_CTRL_VREF_NORMAL_PWR 0x00000000u
#define CYVAL_SAR_PWR_CTRL_VREF_HALF_PWR 0x00000001u
#define CYVAL_SAR_PWR_CTRL_VREF_THIRD_PWR 0x00000002u
#define CYVAL_SAR_PWR_CTRL_VREF_QUARTER_PWR 0x00000003u
#define CYFLD_SAR_SPARE__OFFSET 0x00000010u
#define CYFLD_SAR_SPARE__SIZE 0x00000004u
#define CYFLD_SAR_ICONT_LV__OFFSET 0x00000018u
#define CYFLD_SAR_ICONT_LV__SIZE 0x00000002u
#define CYVAL_SAR_ICONT_LV_NORMAL_PWR 0x00000000u
#define CYVAL_SAR_ICONT_LV_HALF_PWR 0x00000001u
#define CYVAL_SAR_ICONT_LV_MORE_PWR 0x00000002u
#define CYVAL_SAR_ICONT_LV_QUARTER_PWR 0x00000003u
#define CYFLD_SAR_DSI_SYNC_CONFIG__OFFSET 0x0000001cu
#define CYFLD_SAR_DSI_SYNC_CONFIG__SIZE 0x00000001u
#define CYFLD_SAR_DSI_MODE__OFFSET 0x0000001du
#define CYFLD_SAR_DSI_MODE__SIZE 0x00000001u
#define CYFLD_SAR_SWITCH_DISABLE__OFFSET 0x0000001eu
#define CYFLD_SAR_SWITCH_DISABLE__SIZE 0x00000001u
#define CYFLD_SAR_ENABLED__OFFSET 0x0000001fu
#define CYFLD_SAR_ENABLED__SIZE 0x00000001u
#define CYREG_SAR_SAMPLE_CTRL 0x401a0004u
#define CYFLD_SAR_SUB_RESOLUTION__OFFSET 0x00000000u
#define CYFLD_SAR_SUB_RESOLUTION__SIZE 0x00000001u
#define CYVAL_SAR_SUB_RESOLUTION_8B 0x00000000u
#define CYVAL_SAR_SUB_RESOLUTION_10B 0x00000001u
#define CYFLD_SAR_LEFT_ALIGN__OFFSET 0x00000001u
#define CYFLD_SAR_LEFT_ALIGN__SIZE 0x00000001u
#define CYFLD_SAR_SINGLE_ENDED_SIGNED__OFFSET 0x00000002u
#define CYFLD_SAR_SINGLE_ENDED_SIGNED__SIZE 0x00000001u
#define CYVAL_SAR_SINGLE_ENDED_SIGNED_UNSIGNED 0x00000000u
#define CYVAL_SAR_SINGLE_ENDED_SIGNED_SIGNED 0x00000001u
#define CYFLD_SAR_DIFFERENTIAL_SIGNED__OFFSET 0x00000003u
#define CYFLD_SAR_DIFFERENTIAL_SIGNED__SIZE 0x00000001u
#define CYVAL_SAR_DIFFERENTIAL_SIGNED_UNSIGNED 0x00000000u
#define CYVAL_SAR_DIFFERENTIAL_SIGNED_SIGNED 0x00000001u
#define CYFLD_SAR_AVG_CNT__OFFSET 0x00000004u
#define CYFLD_SAR_AVG_CNT__SIZE 0x00000003u
#define CYFLD_SAR_AVG_SHIFT__OFFSET 0x00000007u
#define CYFLD_SAR_AVG_SHIFT__SIZE 0x00000001u
#define CYFLD_SAR_CONTINUOUS__OFFSET 0x00000010u
#define CYFLD_SAR_CONTINUOUS__SIZE 0x00000001u
#define CYFLD_SAR_DSI_TRIGGER_EN__OFFSET 0x00000011u
#define CYFLD_SAR_DSI_TRIGGER_EN__SIZE 0x00000001u
#define CYFLD_SAR_DSI_TRIGGER_LEVEL__OFFSET 0x00000012u
#define CYFLD_SAR_DSI_TRIGGER_LEVEL__SIZE 0x00000001u
#define CYFLD_SAR_DSI_SYNC_TRIGGER__OFFSET 0x00000013u
#define CYFLD_SAR_DSI_SYNC_TRIGGER__SIZE 0x00000001u
#define CYFLD_SAR_EOS_DSI_OUT_EN__OFFSET 0x0000001fu
#define CYFLD_SAR_EOS_DSI_OUT_EN__SIZE 0x00000001u
#define CYREG_SAR_SAMPLE_TIME01 0x401a0010u
#define CYFLD_SAR_SAMPLE_TIME0__OFFSET 0x00000000u
#define CYFLD_SAR_SAMPLE_TIME0__SIZE 0x0000000au
#define CYFLD_SAR_SAMPLE_TIME1__OFFSET 0x00000010u
#define CYFLD_SAR_SAMPLE_TIME1__SIZE 0x0000000au
#define CYREG_SAR_SAMPLE_TIME23 0x401a0014u
#define CYFLD_SAR_SAMPLE_TIME2__OFFSET 0x00000000u
#define CYFLD_SAR_SAMPLE_TIME2__SIZE 0x0000000au
#define CYFLD_SAR_SAMPLE_TIME3__OFFSET 0x00000010u
#define CYFLD_SAR_SAMPLE_TIME3__SIZE 0x0000000au
#define CYREG_SAR_RANGE_THRES 0x401a0018u
#define CYFLD_SAR_RANGE_LOW__OFFSET 0x00000000u
#define CYFLD_SAR_RANGE_LOW__SIZE 0x00000010u
#define CYFLD_SAR_RANGE_HIGH__OFFSET 0x00000010u
#define CYFLD_SAR_RANGE_HIGH__SIZE 0x00000010u
#define CYREG_SAR_RANGE_COND 0x401a001cu
#define CYFLD_SAR_RANGE_COND__OFFSET 0x0000001eu
#define CYFLD_SAR_RANGE_COND__SIZE 0x00000002u
#define CYVAL_SAR_RANGE_COND_BELOW 0x00000000u
#define CYVAL_SAR_RANGE_COND_INSIDE 0x00000001u
#define CYVAL_SAR_RANGE_COND_ABOVE 0x00000002u
#define CYVAL_SAR_RANGE_COND_OUTSIDE 0x00000003u
#define CYREG_SAR_CHAN_EN 0x401a0020u
#define CYFLD_SAR_CHAN_EN__OFFSET 0x00000000u
#define CYFLD_SAR_CHAN_EN__SIZE 0x00000010u
#define CYREG_SAR_START_CTRL 0x401a0024u
#define CYFLD_SAR_FW_TRIGGER__OFFSET 0x00000000u
#define CYFLD_SAR_FW_TRIGGER__SIZE 0x00000001u
#define CYREG_SAR_DFT_CTRL 0x401a0030u
#define CYFLD_SAR_DLY_INC__OFFSET 0x00000000u
#define CYFLD_SAR_DLY_INC__SIZE 0x00000001u
#define CYFLD_SAR_HIZ__OFFSET 0x00000001u
#define CYFLD_SAR_HIZ__SIZE 0x00000001u
#define CYFLD_SAR_DFT_INC__OFFSET 0x00000010u
#define CYFLD_SAR_DFT_INC__SIZE 0x00000004u
#define CYFLD_SAR_DFT_OUTC__OFFSET 0x00000014u
#define CYFLD_SAR_DFT_OUTC__SIZE 0x00000003u
#define CYFLD_SAR_SEL_CSEL_DFT__OFFSET 0x00000018u
#define CYFLD_SAR_SEL_CSEL_DFT__SIZE 0x00000004u
#define CYFLD_SAR_EN_CSEL_DFT__OFFSET 0x0000001cu
#define CYFLD_SAR_EN_CSEL_DFT__SIZE 0x00000001u
#define CYFLD_SAR_DCEN__OFFSET 0x0000001du
#define CYFLD_SAR_DCEN__SIZE 0x00000001u
#define CYFLD_SAR_ADFT_OVERRIDE__OFFSET 0x0000001fu
#define CYFLD_SAR_ADFT_OVERRIDE__SIZE 0x00000001u
#define CYREG_SAR_CHAN_CONFIG00 0x401a0080u
#define CYFLD_SAR_PIN_ADDR__OFFSET 0x00000000u
#define CYFLD_SAR_PIN_ADDR__SIZE 0x00000003u
#define CYFLD_SAR_PORT_ADDR__OFFSET 0x00000004u
#define CYFLD_SAR_PORT_ADDR__SIZE 0x00000003u
#define CYVAL_SAR_PORT_ADDR_SARMUX 0x00000000u
#define CYVAL_SAR_PORT_ADDR_CTB0 0x00000001u
#define CYVAL_SAR_PORT_ADDR_CTB1 0x00000002u
#define CYVAL_SAR_PORT_ADDR_CTB2 0x00000003u
#define CYVAL_SAR_PORT_ADDR_CTB3 0x00000004u
#define CYVAL_SAR_PORT_ADDR_AROUTE_VIRT 0x00000006u
#define CYVAL_SAR_PORT_ADDR_SARMUX_VIRT 0x00000007u
#define CYFLD_SAR_DIFFERENTIAL_EN__OFFSET 0x00000008u
#define CYFLD_SAR_DIFFERENTIAL_EN__SIZE 0x00000001u
#define CYFLD_SAR_RESOLUTION__OFFSET 0x00000009u
#define CYFLD_SAR_RESOLUTION__SIZE 0x00000001u
#define CYVAL_SAR_RESOLUTION_12B 0x00000000u
#define CYVAL_SAR_RESOLUTION_SUBRES 0x00000001u
#define CYFLD_SAR_AVG_EN__OFFSET 0x0000000au
#define CYFLD_SAR_AVG_EN__SIZE 0x00000001u
#define CYFLD_SAR_SAMPLE_TIME_SEL__OFFSET 0x0000000cu
#define CYFLD_SAR_SAMPLE_TIME_SEL__SIZE 0x00000002u
#define CYFLD_SAR_DSI_OUT_EN__OFFSET 0x0000001fu
#define CYFLD_SAR_DSI_OUT_EN__SIZE 0x00000001u
#define CYREG_SAR_CHAN_CONFIG01 0x401a0084u
#define CYREG_SAR_CHAN_CONFIG02 0x401a0088u
#define CYREG_SAR_CHAN_CONFIG03 0x401a008cu
#define CYREG_SAR_CHAN_CONFIG04 0x401a0090u
#define CYREG_SAR_CHAN_CONFIG05 0x401a0094u
#define CYREG_SAR_CHAN_CONFIG06 0x401a0098u
#define CYREG_SAR_CHAN_CONFIG07 0x401a009cu
#define CYREG_SAR_CHAN_WORK00 0x401a0100u
#define CYFLD_SAR_WORK__OFFSET 0x00000000u
#define CYFLD_SAR_WORK__SIZE 0x00000010u
#define CYFLD_SAR_CHAN_WORK_VALID_MIR__OFFSET 0x0000001fu
#define CYFLD_SAR_CHAN_WORK_VALID_MIR__SIZE 0x00000001u
#define CYREG_SAR_CHAN_WORK01 0x401a0104u
#define CYREG_SAR_CHAN_WORK02 0x401a0108u
#define CYREG_SAR_CHAN_WORK03 0x401a010cu
#define CYREG_SAR_CHAN_WORK04 0x401a0110u
#define CYREG_SAR_CHAN_WORK05 0x401a0114u
#define CYREG_SAR_CHAN_WORK06 0x401a0118u
#define CYREG_SAR_CHAN_WORK07 0x401a011cu
#define CYREG_SAR_CHAN_RESULT00 0x401a0180u
#define CYFLD_SAR_RESULT__OFFSET 0x00000000u
#define CYFLD_SAR_RESULT__SIZE 0x00000010u
#define CYFLD_SAR_SATURATE_INTR_MIR__OFFSET 0x0000001du
#define CYFLD_SAR_SATURATE_INTR_MIR__SIZE 0x00000001u
#define CYFLD_SAR_RANGE_INTR_MIR__OFFSET 0x0000001eu
#define CYFLD_SAR_RANGE_INTR_MIR__SIZE 0x00000001u
#define CYFLD_SAR_CHAN_RESULT_VALID_MIR__OFFSET 0x0000001fu
#define CYFLD_SAR_CHAN_RESULT_VALID_MIR__SIZE 0x00000001u
#define CYREG_SAR_CHAN_RESULT01 0x401a0184u
#define CYREG_SAR_CHAN_RESULT02 0x401a0188u
#define CYREG_SAR_CHAN_RESULT03 0x401a018cu
#define CYREG_SAR_CHAN_RESULT04 0x401a0190u
#define CYREG_SAR_CHAN_RESULT05 0x401a0194u
#define CYREG_SAR_CHAN_RESULT06 0x401a0198u
#define CYREG_SAR_CHAN_RESULT07 0x401a019cu
#define CYREG_SAR_CHAN_WORK_VALID 0x401a0200u
#define CYFLD_SAR_CHAN_WORK_VALID__OFFSET 0x00000000u
#define CYFLD_SAR_CHAN_WORK_VALID__SIZE 0x00000010u
#define CYREG_SAR_CHAN_RESULT_VALID 0x401a0204u
#define CYFLD_SAR_CHAN_RESULT_VALID__OFFSET 0x00000000u
#define CYFLD_SAR_CHAN_RESULT_VALID__SIZE 0x00000010u
#define CYREG_SAR_STATUS 0x401a0208u
#define CYFLD_SAR_CUR_CHAN__OFFSET 0x00000000u
#define CYFLD_SAR_CUR_CHAN__SIZE 0x00000005u
#define CYFLD_SAR_SW_VREF_NEG__OFFSET 0x0000001eu
#define CYFLD_SAR_SW_VREF_NEG__SIZE 0x00000001u
#define CYFLD_SAR_BUSY__OFFSET 0x0000001fu
#define CYFLD_SAR_BUSY__SIZE 0x00000001u
#define CYREG_SAR_AVG_STAT 0x401a020cu
#define CYFLD_SAR_CUR_AVG_ACCU__OFFSET 0x00000000u
#define CYFLD_SAR_CUR_AVG_ACCU__SIZE 0x00000014u
#define CYFLD_SAR_CUR_AVG_CNT__OFFSET 0x00000018u
#define CYFLD_SAR_CUR_AVG_CNT__SIZE 0x00000008u
#define CYREG_SAR_INTR 0x401a0210u
#define CYFLD_SAR_EOS_INTR__OFFSET 0x00000000u
#define CYFLD_SAR_EOS_INTR__SIZE 0x00000001u
#define CYFLD_SAR_OVERFLOW_INTR__OFFSET 0x00000001u
#define CYFLD_SAR_OVERFLOW_INTR__SIZE 0x00000001u
#define CYFLD_SAR_FW_COLLISION_INTR__OFFSET 0x00000002u
#define CYFLD_SAR_FW_COLLISION_INTR__SIZE 0x00000001u
#define CYFLD_SAR_DSI_COLLISION_INTR__OFFSET 0x00000003u
#define CYFLD_SAR_DSI_COLLISION_INTR__SIZE 0x00000001u
#define CYFLD_SAR_INJ_EOC_INTR__OFFSET 0x00000004u
#define CYFLD_SAR_INJ_EOC_INTR__SIZE 0x00000001u
#define CYFLD_SAR_INJ_SATURATE_INTR__OFFSET 0x00000005u
#define CYFLD_SAR_INJ_SATURATE_INTR__SIZE 0x00000001u
#define CYFLD_SAR_INJ_RANGE_INTR__OFFSET 0x00000006u
#define CYFLD_SAR_INJ_RANGE_INTR__SIZE 0x00000001u
#define CYFLD_SAR_INJ_COLLISION_INTR__OFFSET 0x00000007u
#define CYFLD_SAR_INJ_COLLISION_INTR__SIZE 0x00000001u
#define CYREG_SAR_INTR_SET 0x401a0214u
#define CYFLD_SAR_EOS_SET__OFFSET 0x00000000u
#define CYFLD_SAR_EOS_SET__SIZE 0x00000001u
#define CYFLD_SAR_OVERFLOW_SET__OFFSET 0x00000001u
#define CYFLD_SAR_OVERFLOW_SET__SIZE 0x00000001u
#define CYFLD_SAR_FW_COLLISION_SET__OFFSET 0x00000002u
#define CYFLD_SAR_FW_COLLISION_SET__SIZE 0x00000001u
#define CYFLD_SAR_DSI_COLLISION_SET__OFFSET 0x00000003u
#define CYFLD_SAR_DSI_COLLISION_SET__SIZE 0x00000001u
#define CYFLD_SAR_INJ_EOC_SET__OFFSET 0x00000004u
#define CYFLD_SAR_INJ_EOC_SET__SIZE 0x00000001u
#define CYFLD_SAR_INJ_SATURATE_SET__OFFSET 0x00000005u
#define CYFLD_SAR_INJ_SATURATE_SET__SIZE 0x00000001u
#define CYFLD_SAR_INJ_RANGE_SET__OFFSET 0x00000006u
#define CYFLD_SAR_INJ_RANGE_SET__SIZE 0x00000001u
#define CYFLD_SAR_INJ_COLLISION_SET__OFFSET 0x00000007u
#define CYFLD_SAR_INJ_COLLISION_SET__SIZE 0x00000001u
#define CYREG_SAR_INTR_MASK 0x401a0218u
#define CYFLD_SAR_EOS_MASK__OFFSET 0x00000000u
#define CYFLD_SAR_EOS_MASK__SIZE 0x00000001u
#define CYFLD_SAR_OVERFLOW_MASK__OFFSET 0x00000001u
#define CYFLD_SAR_OVERFLOW_MASK__SIZE 0x00000001u
#define CYFLD_SAR_FW_COLLISION_MASK__OFFSET 0x00000002u
#define CYFLD_SAR_FW_COLLISION_MASK__SIZE 0x00000001u
#define CYFLD_SAR_DSI_COLLISION_MASK__OFFSET 0x00000003u
#define CYFLD_SAR_DSI_COLLISION_MASK__SIZE 0x00000001u
#define CYFLD_SAR_INJ_EOC_MASK__OFFSET 0x00000004u
#define CYFLD_SAR_INJ_EOC_MASK__SIZE 0x00000001u
#define CYFLD_SAR_INJ_SATURATE_MASK__OFFSET 0x00000005u
#define CYFLD_SAR_INJ_SATURATE_MASK__SIZE 0x00000001u
#define CYFLD_SAR_INJ_RANGE_MASK__OFFSET 0x00000006u
#define CYFLD_SAR_INJ_RANGE_MASK__SIZE 0x00000001u
#define CYFLD_SAR_INJ_COLLISION_MASK__OFFSET 0x00000007u
#define CYFLD_SAR_INJ_COLLISION_MASK__SIZE 0x00000001u
#define CYREG_SAR_INTR_MASKED 0x401a021cu
#define CYFLD_SAR_EOS_MASKED__OFFSET 0x00000000u
#define CYFLD_SAR_EOS_MASKED__SIZE 0x00000001u
#define CYFLD_SAR_OVERFLOW_MASKED__OFFSET 0x00000001u
#define CYFLD_SAR_OVERFLOW_MASKED__SIZE 0x00000001u
#define CYFLD_SAR_FW_COLLISION_MASKED__OFFSET 0x00000002u
#define CYFLD_SAR_FW_COLLISION_MASKED__SIZE 0x00000001u
#define CYFLD_SAR_DSI_COLLISION_MASKED__OFFSET 0x00000003u
#define CYFLD_SAR_DSI_COLLISION_MASKED__SIZE 0x00000001u
#define CYFLD_SAR_INJ_EOC_MASKED__OFFSET 0x00000004u
#define CYFLD_SAR_INJ_EOC_MASKED__SIZE 0x00000001u
#define CYFLD_SAR_INJ_SATURATE_MASKED__OFFSET 0x00000005u
#define CYFLD_SAR_INJ_SATURATE_MASKED__SIZE 0x00000001u
#define CYFLD_SAR_INJ_RANGE_MASKED__OFFSET 0x00000006u
#define CYFLD_SAR_INJ_RANGE_MASKED__SIZE 0x00000001u
#define CYFLD_SAR_INJ_COLLISION_MASKED__OFFSET 0x00000007u
#define CYFLD_SAR_INJ_COLLISION_MASKED__SIZE 0x00000001u
#define CYREG_SAR_SATURATE_INTR 0x401a0220u
#define CYFLD_SAR_SATURATE_INTR__OFFSET 0x00000000u
#define CYFLD_SAR_SATURATE_INTR__SIZE 0x00000010u
#define CYREG_SAR_SATURATE_INTR_SET 0x401a0224u
#define CYFLD_SAR_SATURATE_SET__OFFSET 0x00000000u
#define CYFLD_SAR_SATURATE_SET__SIZE 0x00000010u
#define CYREG_SAR_SATURATE_INTR_MASK 0x401a0228u
#define CYFLD_SAR_SATURATE_MASK__OFFSET 0x00000000u
#define CYFLD_SAR_SATURATE_MASK__SIZE 0x00000010u
#define CYREG_SAR_SATURATE_INTR_MASKED 0x401a022cu
#define CYFLD_SAR_SATURATE_MASKED__OFFSET 0x00000000u
#define CYFLD_SAR_SATURATE_MASKED__SIZE 0x00000010u
#define CYREG_SAR_RANGE_INTR 0x401a0230u
#define CYFLD_SAR_RANGE_INTR__OFFSET 0x00000000u
#define CYFLD_SAR_RANGE_INTR__SIZE 0x00000010u
#define CYREG_SAR_RANGE_INTR_SET 0x401a0234u
#define CYFLD_SAR_RANGE_SET__OFFSET 0x00000000u
#define CYFLD_SAR_RANGE_SET__SIZE 0x00000010u
#define CYREG_SAR_RANGE_INTR_MASK 0x401a0238u
#define CYFLD_SAR_RANGE_MASK__OFFSET 0x00000000u
#define CYFLD_SAR_RANGE_MASK__SIZE 0x00000010u
#define CYREG_SAR_RANGE_INTR_MASKED 0x401a023cu
#define CYFLD_SAR_RANGE_MASKED__OFFSET 0x00000000u
#define CYFLD_SAR_RANGE_MASKED__SIZE 0x00000010u
#define CYREG_SAR_INTR_CAUSE 0x401a0240u
#define CYFLD_SAR_EOS_MASKED_MIR__OFFSET 0x00000000u
#define CYFLD_SAR_EOS_MASKED_MIR__SIZE 0x00000001u
#define CYFLD_SAR_OVERFLOW_MASKED_MIR__OFFSET 0x00000001u
#define CYFLD_SAR_OVERFLOW_MASKED_MIR__SIZE 0x00000001u
#define CYFLD_SAR_FW_COLLISION_MASKED_MIR__OFFSET 0x00000002u
#define CYFLD_SAR_FW_COLLISION_MASKED_MIR__SIZE 0x00000001u
#define CYFLD_SAR_DSI_COLLISION_MASKED_MIR__OFFSET 0x00000003u
#define CYFLD_SAR_DSI_COLLISION_MASKED_MIR__SIZE 0x00000001u
#define CYFLD_SAR_INJ_EOC_MASKED_MIR__OFFSET 0x00000004u
#define CYFLD_SAR_INJ_EOC_MASKED_MIR__SIZE 0x00000001u
#define CYFLD_SAR_INJ_SATURATE_MASKED_MIR__OFFSET 0x00000005u
#define CYFLD_SAR_INJ_SATURATE_MASKED_MIR__SIZE 0x00000001u
#define CYFLD_SAR_INJ_RANGE_MASKED_MIR__OFFSET 0x00000006u
#define CYFLD_SAR_INJ_RANGE_MASKED_MIR__SIZE 0x00000001u
#define CYFLD_SAR_INJ_COLLISION_MASKED_MIR__OFFSET 0x00000007u
#define CYFLD_SAR_INJ_COLLISION_MASKED_MIR__SIZE 0x00000001u
#define CYFLD_SAR_SATURATE_MASKED_RED__OFFSET 0x0000001eu
#define CYFLD_SAR_SATURATE_MASKED_RED__SIZE 0x00000001u
#define CYFLD_SAR_RANGE_MASKED_RED__OFFSET 0x0000001fu
#define CYFLD_SAR_RANGE_MASKED_RED__SIZE 0x00000001u
#define CYREG_SAR_INJ_CHAN_CONFIG 0x401a0280u
#define CYFLD_SAR_INJ_PIN_ADDR__OFFSET 0x00000000u
#define CYFLD_SAR_INJ_PIN_ADDR__SIZE 0x00000003u
#define CYFLD_SAR_INJ_PORT_ADDR__OFFSET 0x00000004u
#define CYFLD_SAR_INJ_PORT_ADDR__SIZE 0x00000003u
#define CYVAL_SAR_INJ_PORT_ADDR_SARMUX 0x00000000u
#define CYVAL_SAR_INJ_PORT_ADDR_CTB0 0x00000001u
#define CYVAL_SAR_INJ_PORT_ADDR_CTB1 0x00000002u
#define CYVAL_SAR_INJ_PORT_ADDR_CTB2 0x00000003u
#define CYVAL_SAR_INJ_PORT_ADDR_CTB3 0x00000004u
#define CYVAL_SAR_INJ_PORT_ADDR_AROUTE_VIRT 0x00000006u
#define CYVAL_SAR_INJ_PORT_ADDR_SARMUX_VIRT 0x00000007u
#define CYFLD_SAR_INJ_DIFFERENTIAL_EN__OFFSET 0x00000008u
#define CYFLD_SAR_INJ_DIFFERENTIAL_EN__SIZE 0x00000001u
#define CYFLD_SAR_INJ_RESOLUTION__OFFSET 0x00000009u
#define CYFLD_SAR_INJ_RESOLUTION__SIZE 0x00000001u
#define CYVAL_SAR_INJ_RESOLUTION_12B 0x00000000u
#define CYVAL_SAR_INJ_RESOLUTION_SUBRES 0x00000001u
#define CYFLD_SAR_INJ_AVG_EN__OFFSET 0x0000000au
#define CYFLD_SAR_INJ_AVG_EN__SIZE 0x00000001u
#define CYFLD_SAR_INJ_SAMPLE_TIME_SEL__OFFSET 0x0000000cu
#define CYFLD_SAR_INJ_SAMPLE_TIME_SEL__SIZE 0x00000002u
#define CYFLD_SAR_INJ_TAILGATING__OFFSET 0x0000001eu
#define CYFLD_SAR_INJ_TAILGATING__SIZE 0x00000001u
#define CYFLD_SAR_INJ_START_EN__OFFSET 0x0000001fu
#define CYFLD_SAR_INJ_START_EN__SIZE 0x00000001u
#define CYREG_SAR_INJ_RESULT 0x401a0290u
#define CYFLD_SAR_INJ_RESULT__OFFSET 0x00000000u
#define CYFLD_SAR_INJ_RESULT__SIZE 0x00000010u
#define CYFLD_SAR_INJ_COLLISION_INTR_MIR__OFFSET 0x0000001cu
#define CYFLD_SAR_INJ_COLLISION_INTR_MIR__SIZE 0x00000001u
#define CYFLD_SAR_INJ_SATURATE_INTR_MIR__OFFSET 0x0000001du
#define CYFLD_SAR_INJ_SATURATE_INTR_MIR__SIZE 0x00000001u
#define CYFLD_SAR_INJ_RANGE_INTR_MIR__OFFSET 0x0000001eu
#define CYFLD_SAR_INJ_RANGE_INTR_MIR__SIZE 0x00000001u
#define CYFLD_SAR_INJ_EOC_INTR_MIR__OFFSET 0x0000001fu
#define CYFLD_SAR_INJ_EOC_INTR_MIR__SIZE 0x00000001u
#define CYREG_SAR_MUX_SWITCH0 0x401a0300u
#define CYFLD_SAR_MUX_FW_P0_VPLUS__OFFSET 0x00000000u
#define CYFLD_SAR_MUX_FW_P0_VPLUS__SIZE 0x00000001u
#define CYFLD_SAR_MUX_FW_P1_VPLUS__OFFSET 0x00000001u
#define CYFLD_SAR_MUX_FW_P1_VPLUS__SIZE 0x00000001u
#define CYFLD_SAR_MUX_FW_P2_VPLUS__OFFSET 0x00000002u
#define CYFLD_SAR_MUX_FW_P2_VPLUS__SIZE 0x00000001u
#define CYFLD_SAR_MUX_FW_P3_VPLUS__OFFSET 0x00000003u
#define CYFLD_SAR_MUX_FW_P3_VPLUS__SIZE 0x00000001u
#define CYFLD_SAR_MUX_FW_P4_VPLUS__OFFSET 0x00000004u
#define CYFLD_SAR_MUX_FW_P4_VPLUS__SIZE 0x00000001u
#define CYFLD_SAR_MUX_FW_P5_VPLUS__OFFSET 0x00000005u
#define CYFLD_SAR_MUX_FW_P5_VPLUS__SIZE 0x00000001u
#define CYFLD_SAR_MUX_FW_P6_VPLUS__OFFSET 0x00000006u
#define CYFLD_SAR_MUX_FW_P6_VPLUS__SIZE 0x00000001u
#define CYFLD_SAR_MUX_FW_P7_VPLUS__OFFSET 0x00000007u
#define CYFLD_SAR_MUX_FW_P7_VPLUS__SIZE 0x00000001u
#define CYFLD_SAR_MUX_FW_P0_VMINUS__OFFSET 0x00000008u
#define CYFLD_SAR_MUX_FW_P0_VMINUS__SIZE 0x00000001u
#define CYFLD_SAR_MUX_FW_P1_VMINUS__OFFSET 0x00000009u
#define CYFLD_SAR_MUX_FW_P1_VMINUS__SIZE 0x00000001u
#define CYFLD_SAR_MUX_FW_P2_VMINUS__OFFSET 0x0000000au
#define CYFLD_SAR_MUX_FW_P2_VMINUS__SIZE 0x00000001u
#define CYFLD_SAR_MUX_FW_P3_VMINUS__OFFSET 0x0000000bu
#define CYFLD_SAR_MUX_FW_P3_VMINUS__SIZE 0x00000001u
#define CYFLD_SAR_MUX_FW_P4_VMINUS__OFFSET 0x0000000cu
#define CYFLD_SAR_MUX_FW_P4_VMINUS__SIZE 0x00000001u
#define CYFLD_SAR_MUX_FW_P5_VMINUS__OFFSET 0x0000000du
#define CYFLD_SAR_MUX_FW_P5_VMINUS__SIZE 0x00000001u
#define CYFLD_SAR_MUX_FW_P6_VMINUS__OFFSET 0x0000000eu
#define CYFLD_SAR_MUX_FW_P6_VMINUS__SIZE 0x00000001u
#define CYFLD_SAR_MUX_FW_P7_VMINUS__OFFSET 0x0000000fu
#define CYFLD_SAR_MUX_FW_P7_VMINUS__SIZE 0x00000001u
#define CYFLD_SAR_MUX_FW_VSSA_VMINUS__OFFSET 0x00000010u
#define CYFLD_SAR_MUX_FW_VSSA_VMINUS__SIZE 0x00000001u
#define CYFLD_SAR_MUX_FW_TEMP_VPLUS__OFFSET 0x00000011u
#define CYFLD_SAR_MUX_FW_TEMP_VPLUS__SIZE 0x00000001u
#define CYFLD_SAR_MUX_FW_AMUXBUSA_VPLUS__OFFSET 0x00000012u
#define CYFLD_SAR_MUX_FW_AMUXBUSA_VPLUS__SIZE 0x00000001u
#define CYFLD_SAR_MUX_FW_AMUXBUSB_VPLUS__OFFSET 0x00000013u
#define CYFLD_SAR_MUX_FW_AMUXBUSB_VPLUS__SIZE 0x00000001u
#define CYFLD_SAR_MUX_FW_AMUXBUSA_VMINUS__OFFSET 0x00000014u
#define CYFLD_SAR_MUX_FW_AMUXBUSA_VMINUS__SIZE 0x00000001u
#define CYFLD_SAR_MUX_FW_AMUXBUSB_VMINUS__OFFSET 0x00000015u
#define CYFLD_SAR_MUX_FW_AMUXBUSB_VMINUS__SIZE 0x00000001u
#define CYFLD_SAR_MUX_FW_SARBUS0_VPLUS__OFFSET 0x00000016u
#define CYFLD_SAR_MUX_FW_SARBUS0_VPLUS__SIZE 0x00000001u
#define CYFLD_SAR_MUX_FW_SARBUS1_VPLUS__OFFSET 0x00000017u
#define CYFLD_SAR_MUX_FW_SARBUS1_VPLUS__SIZE 0x00000001u
#define CYFLD_SAR_MUX_FW_SARBUS0_VMINUS__OFFSET 0x00000018u
#define CYFLD_SAR_MUX_FW_SARBUS0_VMINUS__SIZE 0x00000001u
#define CYFLD_SAR_MUX_FW_SARBUS1_VMINUS__OFFSET 0x00000019u
#define CYFLD_SAR_MUX_FW_SARBUS1_VMINUS__SIZE 0x00000001u
#define CYFLD_SAR_MUX_FW_P4_COREIO0__OFFSET 0x0000001au
#define CYFLD_SAR_MUX_FW_P4_COREIO0__SIZE 0x00000001u
#define CYFLD_SAR_MUX_FW_P5_COREIO1__OFFSET 0x0000001bu
#define CYFLD_SAR_MUX_FW_P5_COREIO1__SIZE 0x00000001u
#define CYFLD_SAR_MUX_FW_P6_COREIO2__OFFSET 0x0000001cu
#define CYFLD_SAR_MUX_FW_P6_COREIO2__SIZE 0x00000001u
#define CYFLD_SAR_MUX_FW_P7_COREIO3__OFFSET 0x0000001du
#define CYFLD_SAR_MUX_FW_P7_COREIO3__SIZE 0x00000001u
#define CYREG_SAR_MUX_SWITCH_CLEAR0 0x401a0304u
#define CYREG_SAR_MUX_SWITCH1 0x401a0308u
#define CYFLD_SAR_MUX_FW_P4_DFT_INP__OFFSET 0x00000000u
#define CYFLD_SAR_MUX_FW_P4_DFT_INP__SIZE 0x00000001u
#define CYFLD_SAR_MUX_FW_P5_DFT_INM__OFFSET 0x00000001u
#define CYFLD_SAR_MUX_FW_P5_DFT_INM__SIZE 0x00000001u
#define CYFLD_SAR_MUX_FW_ADFT0_SARBUS0__OFFSET 0x00000002u
#define CYFLD_SAR_MUX_FW_ADFT0_SARBUS0__SIZE 0x00000001u
#define CYFLD_SAR_MUX_FW_ADFT1_SARBUS1__OFFSET 0x00000003u
#define CYFLD_SAR_MUX_FW_ADFT1_SARBUS1__SIZE 0x00000001u
#define CYREG_SAR_MUX_SWITCH_CLEAR1 0x401a030cu
#define CYREG_SAR_MUX_SWITCH_HW_CTRL 0x401a0340u
#define CYFLD_SAR_MUX_HW_CTRL_P0__OFFSET 0x00000000u
#define CYFLD_SAR_MUX_HW_CTRL_P0__SIZE 0x00000001u
#define CYFLD_SAR_MUX_HW_CTRL_P1__OFFSET 0x00000001u
#define CYFLD_SAR_MUX_HW_CTRL_P1__SIZE 0x00000001u
#define CYFLD_SAR_MUX_HW_CTRL_P2__OFFSET 0x00000002u
#define CYFLD_SAR_MUX_HW_CTRL_P2__SIZE 0x00000001u
#define CYFLD_SAR_MUX_HW_CTRL_P3__OFFSET 0x00000003u
#define CYFLD_SAR_MUX_HW_CTRL_P3__SIZE 0x00000001u
#define CYFLD_SAR_MUX_HW_CTRL_P4__OFFSET 0x00000004u
#define CYFLD_SAR_MUX_HW_CTRL_P4__SIZE 0x00000001u
#define CYFLD_SAR_MUX_HW_CTRL_P5__OFFSET 0x00000005u
#define CYFLD_SAR_MUX_HW_CTRL_P5__SIZE 0x00000001u
#define CYFLD_SAR_MUX_HW_CTRL_P6__OFFSET 0x00000006u
#define CYFLD_SAR_MUX_HW_CTRL_P6__SIZE 0x00000001u
#define CYFLD_SAR_MUX_HW_CTRL_P7__OFFSET 0x00000007u
#define CYFLD_SAR_MUX_HW_CTRL_P7__SIZE 0x00000001u
#define CYFLD_SAR_MUX_HW_CTRL_VSSA__OFFSET 0x00000010u
#define CYFLD_SAR_MUX_HW_CTRL_VSSA__SIZE 0x00000001u
#define CYFLD_SAR_MUX_HW_CTRL_TEMP__OFFSET 0x00000011u
#define CYFLD_SAR_MUX_HW_CTRL_TEMP__SIZE 0x00000001u
#define CYFLD_SAR_MUX_HW_CTRL_AMUXBUSA__OFFSET 0x00000012u
#define CYFLD_SAR_MUX_HW_CTRL_AMUXBUSA__SIZE 0x00000001u
#define CYFLD_SAR_MUX_HW_CTRL_AMUXBUSB__OFFSET 0x00000013u
#define CYFLD_SAR_MUX_HW_CTRL_AMUXBUSB__SIZE 0x00000001u
#define CYFLD_SAR_MUX_HW_CTRL_SARBUS0__OFFSET 0x00000016u
#define CYFLD_SAR_MUX_HW_CTRL_SARBUS0__SIZE 0x00000001u
#define CYFLD_SAR_MUX_HW_CTRL_SARBUS1__OFFSET 0x00000017u
#define CYFLD_SAR_MUX_HW_CTRL_SARBUS1__SIZE 0x00000001u
#define CYREG_SAR_MUX_SWITCH_STATUS 0x401a0348u
#define CYREG_SAR_PUMP_CTRL 0x401a0380u
#define CYFLD_SAR_CLOCK_SEL__OFFSET 0x00000000u
#define CYFLD_SAR_CLOCK_SEL__SIZE 0x00000001u
#define CYREG_SAR_ANA_TRIM 0x401a0f00u
#define CYFLD_SAR_CAP_TRIM__OFFSET 0x00000000u
#define CYFLD_SAR_CAP_TRIM__SIZE 0x00000003u
#define CYFLD_SAR_TRIMUNIT__OFFSET 0x00000003u
#define CYFLD_SAR_TRIMUNIT__SIZE 0x00000001u
#define CYREG_SAR_WOUNDING 0x401a0f04u
#define CYFLD_SAR_WOUND_RESOLUTION__OFFSET 0x00000000u
#define CYFLD_SAR_WOUND_RESOLUTION__SIZE 0x00000002u
#define CYVAL_SAR_WOUND_RESOLUTION_12BIT 0x00000000u
#define CYVAL_SAR_WOUND_RESOLUTION_10BIT 0x00000001u
#define CYVAL_SAR_WOUND_RESOLUTION_8BIT 0x00000002u
#define CYVAL_SAR_WOUND_RESOLUTION_8BIT_TOO 0x00000003u
#define CYDEV_CM0_BASE 0xe0000000u
#define CYDEV_CM0_SIZE 0x00100000u
#define CYREG_CM0_DWT_PID4 0xe0001fd0u
#define CYFLD_CM0_VALUE__OFFSET 0x00000000u
#define CYFLD_CM0_VALUE__SIZE 0x00000020u
#define CYREG_CM0_DWT_PID0 0xe0001fe0u
#define CYREG_CM0_DWT_PID1 0xe0001fe4u
#define CYREG_CM0_DWT_PID2 0xe0001fe8u
#define CYREG_CM0_DWT_PID3 0xe0001fecu
#define CYREG_CM0_DWT_CID0 0xe0001ff0u
#define CYREG_CM0_DWT_CID1 0xe0001ff4u
#define CYREG_CM0_DWT_CID2 0xe0001ff8u
#define CYREG_CM0_DWT_CID3 0xe0001ffcu
#define CYREG_CM0_BP_PID4 0xe0002fd0u
#define CYREG_CM0_BP_PID0 0xe0002fe0u
#define CYREG_CM0_BP_PID1 0xe0002fe4u
#define CYREG_CM0_BP_PID2 0xe0002fe8u
#define CYREG_CM0_BP_PID3 0xe0002fecu
#define CYREG_CM0_BP_CID0 0xe0002ff0u
#define CYREG_CM0_BP_CID1 0xe0002ff4u
#define CYREG_CM0_BP_CID2 0xe0002ff8u
#define CYREG_CM0_BP_CID3 0xe0002ffcu
#define CYREG_CM0_SYST_CSR 0xe000e010u
#define CYFLD_CM0_ENABLE__OFFSET 0x00000000u
#define CYFLD_CM0_ENABLE__SIZE 0x00000001u
#define CYFLD_CM0_TICKINT__OFFSET 0x00000001u
#define CYFLD_CM0_TICKINT__SIZE 0x00000001u
#define CYFLD_CM0_CLKSOURCE__OFFSET 0x00000002u
#define CYFLD_CM0_CLKSOURCE__SIZE 0x00000001u
#define CYFLD_CM0_COUNTFLAG__OFFSET 0x00000010u
#define CYFLD_CM0_COUNTFLAG__SIZE 0x00000001u
#define CYREG_CM0_SYST_RVR 0xe000e014u
#define CYFLD_CM0_RELOAD__OFFSET 0x00000000u
#define CYFLD_CM0_RELOAD__SIZE 0x00000018u
#define CYREG_CM0_SYST_CVR 0xe000e018u
#define CYFLD_CM0_CURRENT__OFFSET 0x00000000u
#define CYFLD_CM0_CURRENT__SIZE 0x00000018u
#define CYREG_CM0_SYST_CALIB 0xe000e01cu
#define CYFLD_CM0_TENMS__OFFSET 0x00000000u
#define CYFLD_CM0_TENMS__SIZE 0x00000018u
#define CYFLD_CM0_SKEW__OFFSET 0x0000001eu
#define CYFLD_CM0_SKEW__SIZE 0x00000001u
#define CYFLD_CM0_NOREF__OFFSET 0x0000001fu
#define CYFLD_CM0_NOREF__SIZE 0x00000001u
#define CYREG_CM0_ISER 0xe000e100u
#define CYFLD_CM0_SETENA__OFFSET 0x00000000u
#define CYFLD_CM0_SETENA__SIZE 0x00000020u
#define CYREG_CM0_ICER 0xe000e180u
#define CYFLD_CM0_CLRENA__OFFSET 0x00000000u
#define CYFLD_CM0_CLRENA__SIZE 0x00000020u
#define CYREG_CM0_ISPR 0xe000e200u
#define CYFLD_CM0_SETPEND__OFFSET 0x00000000u
#define CYFLD_CM0_SETPEND__SIZE 0x00000020u
#define CYREG_CM0_ICPR 0xe000e280u
#define CYFLD_CM0_CLRPEND__OFFSET 0x00000000u
#define CYFLD_CM0_CLRPEND__SIZE 0x00000020u
#define CYREG_CM0_IPR0 0xe000e400u
#define CYFLD_CM0_PRI_N0__OFFSET 0x00000006u
#define CYFLD_CM0_PRI_N0__SIZE 0x00000002u
#define CYFLD_CM0_PRI_N1__OFFSET 0x0000000eu
#define CYFLD_CM0_PRI_N1__SIZE 0x00000002u
#define CYFLD_CM0_PRI_N2__OFFSET 0x00000016u
#define CYFLD_CM0_PRI_N2__SIZE 0x00000002u
#define CYFLD_CM0_PRI_N3__OFFSET 0x0000001eu
#define CYFLD_CM0_PRI_N3__SIZE 0x00000002u
#define CYREG_CM0_IPR1 0xe000e404u
#define CYREG_CM0_IPR2 0xe000e408u
#define CYREG_CM0_IPR3 0xe000e40cu
#define CYREG_CM0_IPR4 0xe000e410u
#define CYREG_CM0_IPR5 0xe000e414u
#define CYREG_CM0_IPR6 0xe000e418u
#define CYREG_CM0_IPR7 0xe000e41cu
#define CYREG_CM0_CPUID 0xe000ed00u
#define CYFLD_CM0_REVISION__OFFSET 0x00000000u
#define CYFLD_CM0_REVISION__SIZE 0x00000004u
#define CYFLD_CM0_PARTNO__OFFSET 0x00000004u
#define CYFLD_CM0_PARTNO__SIZE 0x0000000cu
#define CYFLD_CM0_CONSTANT__OFFSET 0x00000010u
#define CYFLD_CM0_CONSTANT__SIZE 0x00000004u
#define CYFLD_CM0_VARIANT__OFFSET 0x00000014u
#define CYFLD_CM0_VARIANT__SIZE 0x00000004u
#define CYFLD_CM0_IMPLEMENTER__OFFSET 0x00000018u
#define CYFLD_CM0_IMPLEMENTER__SIZE 0x00000008u
#define CYREG_CM0_ICSR 0xe000ed04u
#define CYFLD_CM0_VECTACTIVE__OFFSET 0x00000000u
#define CYFLD_CM0_VECTACTIVE__SIZE 0x00000009u
#define CYFLD_CM0_VECTPENDING__OFFSET 0x0000000cu
#define CYFLD_CM0_VECTPENDING__SIZE 0x00000009u
#define CYFLD_CM0_ISRPENDING__OFFSET 0x00000016u
#define CYFLD_CM0_ISRPENDING__SIZE 0x00000001u
#define CYFLD_CM0_ISRPREEMPT__OFFSET 0x00000017u
#define CYFLD_CM0_ISRPREEMPT__SIZE 0x00000001u
#define CYFLD_CM0_PENDSTCLR__OFFSET 0x00000019u
#define CYFLD_CM0_PENDSTCLR__SIZE 0x00000001u
#define CYFLD_CM0_PENDSTSETb__OFFSET 0x0000001au
#define CYFLD_CM0_PENDSTSETb__SIZE 0x00000001u
#define CYFLD_CM0_PENDSVCLR__OFFSET 0x0000001bu
#define CYFLD_CM0_PENDSVCLR__SIZE 0x00000001u
#define CYFLD_CM0_PENDSVSET__OFFSET 0x0000001cu
#define CYFLD_CM0_PENDSVSET__SIZE 0x00000001u
#define CYFLD_CM0_NMIPENDSET__OFFSET 0x0000001fu
#define CYFLD_CM0_NMIPENDSET__SIZE 0x00000001u
#define CYREG_CM0_AIRCR 0xe000ed0cu
#define CYFLD_CM0_VECTCLRACTIVE__OFFSET 0x00000001u
#define CYFLD_CM0_VECTCLRACTIVE__SIZE 0x00000001u
#define CYFLD_CM0_SYSRESETREQ__OFFSET 0x00000002u
#define CYFLD_CM0_SYSRESETREQ__SIZE 0x00000001u
#define CYFLD_CM0_ENDIANNESS__OFFSET 0x0000000fu
#define CYFLD_CM0_ENDIANNESS__SIZE 0x00000001u
#define CYFLD_CM0_VECTKEY__OFFSET 0x00000010u
#define CYFLD_CM0_VECTKEY__SIZE 0x00000010u
#define CYREG_CM0_SCR 0xe000ed10u
#define CYFLD_CM0_SLEEPONEXIT__OFFSET 0x00000001u
#define CYFLD_CM0_SLEEPONEXIT__SIZE 0x00000001u
#define CYFLD_CM0_SLEEPDEEP__OFFSET 0x00000002u
#define CYFLD_CM0_SLEEPDEEP__SIZE 0x00000001u
#define CYFLD_CM0_SEVONPEND__OFFSET 0x00000004u
#define CYFLD_CM0_SEVONPEND__SIZE 0x00000001u
#define CYREG_CM0_CCR 0xe000ed14u
#define CYFLD_CM0_UNALIGN_TRP__OFFSET 0x00000003u
#define CYFLD_CM0_UNALIGN_TRP__SIZE 0x00000001u
#define CYFLD_CM0_STKALIGN__OFFSET 0x00000009u
#define CYFLD_CM0_STKALIGN__SIZE 0x00000001u
#define CYREG_CM0_SHPR2 0xe000ed1cu
#define CYFLD_CM0_PRI_11__OFFSET 0x0000001eu
#define CYFLD_CM0_PRI_11__SIZE 0x00000002u
#define CYREG_CM0_SHPR3 0xe000ed20u
#define CYFLD_CM0_PRI_14__OFFSET 0x00000016u
#define CYFLD_CM0_PRI_14__SIZE 0x00000002u
#define CYFLD_CM0_PRI_15__OFFSET 0x0000001eu
#define CYFLD_CM0_PRI_15__SIZE 0x00000002u
#define CYREG_CM0_SHCSR 0xe000ed24u
#define CYFLD_CM0_SVCALLPENDED__OFFSET 0x0000000fu
#define CYFLD_CM0_SVCALLPENDED__SIZE 0x00000001u
#define CYREG_CM0_SCS_PID4 0xe000efd0u
#define CYREG_CM0_SCS_PID0 0xe000efe0u
#define CYREG_CM0_SCS_PID1 0xe000efe4u
#define CYREG_CM0_SCS_PID2 0xe000efe8u
#define CYREG_CM0_SCS_PID3 0xe000efecu
#define CYREG_CM0_SCS_CID0 0xe000eff0u
#define CYREG_CM0_SCS_CID1 0xe000eff4u
#define CYREG_CM0_SCS_CID2 0xe000eff8u
#define CYREG_CM0_SCS_CID3 0xe000effcu
#define CYREG_CM0_ROM_SCS 0xe00ff000u
#define CYREG_CM0_ROM_DWT 0xe00ff004u
#define CYREG_CM0_ROM_BPU 0xe00ff008u
#define CYREG_CM0_ROM_END 0xe00ff00cu
#define CYREG_CM0_ROM_CSMT 0xe00fffccu
#define CYREG_CM0_ROM_PID4 0xe00fffd0u
#define CYREG_CM0_ROM_PID0 0xe00fffe0u
#define CYREG_CM0_ROM_PID1 0xe00fffe4u
#define CYREG_CM0_ROM_PID2 0xe00fffe8u
#define CYREG_CM0_ROM_PID3 0xe00fffecu
#define CYREG_CM0_ROM_CID0 0xe00ffff0u
#define CYREG_CM0_ROM_CID1 0xe00ffff4u
#define CYREG_CM0_ROM_CID2 0xe00ffff8u
#define CYREG_CM0_ROM_CID3 0xe00ffffcu
#define CYDEV_CoreSightTable_BASE 0xf0000000u
#define CYDEV_CoreSightTable_SIZE 0x00001000u
#define CYREG_CoreSightTable_DATA_MBASE 0xf0000000u
#define CYREG_CoreSightTable_DATA_MSIZE 0x00001000u
#define CYDEV_FLS_SECTOR_SIZE 0x00008000u
#define CYDEV_FLS_ROW_SIZE 0x00000080u
#endif /* CYDEVICE_TRM_H */
