# Static Timing Analysis

Project : | 1. Basic PWM Kode
Build Time : | 05/26/18 09:50:15
Device : | CY8C4245AXI-483
Temperature : | -40C - 85C
VDDA : | 3.30
VDDD : | 3.30
Voltage : | 3.3

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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section

Clock | Domain | Nominal Frequency | Required Frequency | Maximum Frequency | Violation
--- | --- | --- | --- | --- | ---
CyHFClk | CyHFClk | 24.000 MHz | 24.000 MHz | N/A |
Clock_1 | CyHFClk | 1.000 kHz | 1.000 kHz | 55.723 MHz |
CyILO | CyILO | 32.000 kHz | 32.000 kHz | N/A |
CyIMO | CyIMO | 24.000 MHz | 24.000 MHz | N/A |
CyLFClk | CyLFClk | 32.000 kHz | 32.000 kHz | N/A |
CyRouted1 | CyRouted1 | 24.000 MHz | 24.000 MHz | N/A |
CySysClk | CySysClk | 24.000 MHz | 24.000 MHz | N/A |

+ Register to Register Section
+ Setup Subsection
+ Source Clock : Clock_1 : Positive edge(Required Frequency 1 kHz)
+ Destination Clock : Clock_1 : Positive edge(Required Frequency 1 kHz)
Path Delay Requirement : 1e+006ns(1 kHz)

Source | Destination | FMax | Delay (ns) | Slack (ns) | Violation
--- | --- | --- | --- | --- | ---
\PWM_1:PWMUDB:sP8:pwmdp:u0\/z0_comb | \PWM_1:PWMUDB:sP8:pwmdp:u0\/cs_addr_2 | 55.723 MHz | 17.946 | 999982.054 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
datapathcell1 | U(1,1) | 1 | \PWM_1:PWMUDB:sP8:pwmdp:u0\ | \PWM_1:PWMUDB:sP8:pwmdp:u0\/clock | \PWM_1:PWMUDB:sP8:pwmdp:u0\/z0_comb | 3.850
datapathcell1 | U(1,1) | 1 | \PWM_1:PWMUDB:sP8:pwmdp:u0\ | \PWM_1:PWMUDB:sP8:pwmdp:u0\/z0_comb | \PWM_1:PWMUDB:sP8:pwmdp:u0\/cs_addr_2 | 2.576
datapathcell1 | U(1,1) | 1 | \PWM_1:PWMUDB:sP8:pwmdp:u0\ |  | SETUP | 11.520
Clock |  |  |  |  | Skew | 0.000
\PWM_1:PWMUDB:runmode_enable\/q | \PWM_1:PWMUDB:sP8:pwmdp:u0\/cs_addr_1 | 62.294 MHz | 16.053 | 999983.947 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
macrocell2 | U(1,1) | 1 | \PWM_1:PWMUDB:runmode_enable\ | \PWM_1:PWMUDB:runmode_enable\/clock_0 | \PWM_1:PWMUDB:runmode_enable\/q | 1.250
Route |  | 1 | \PWM_1:PWMUDB:runmode_enable\ | \PWM_1:PWMUDB:runmode_enable\/q | \PWM_1:PWMUDB:sP8:pwmdp:u0\/cs_addr_1 | 3.283
datapathcell1 | U(1,1) | 1 | \PWM_1:PWMUDB:sP8:pwmdp:u0\ |  | SETUP | 11.520
Clock |  |  |  |  | Skew | 0.000
\PWM_1:PWMUDB:sP8:pwmdp:u0\/z0_comb | \PWM_1:PWMUDB:genblk8:stsreg\/status_2 | 73.233 MHz | 13.655 | 999986.345 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
datapathcell1 | U(1,1) | 1 | \PWM_1:PWMUDB:sP8:pwmdp:u0\ | \PWM_1:PWMUDB:sP8:pwmdp:u0\/clock | \PWM_1:PWMUDB:sP8:pwmdp:u0\/z0_comb | 3.850
Route |  | 1 | \PWM_1:PWMUDB:tc_i\ | \PWM_1:PWMUDB:sP8:pwmdp:u0\/z0_comb | \PWM_1:PWMUDB:status_2\/main_1 | 2.582
macrocell1 | U(1,1) | 1 | \PWM_1:PWMUDB:status_2\ | \PWM_1:PWMUDB:status_2\/main_1 | \PWM_1:PWMUDB:status_2\/q | 3.350
Route |  | 1 | \PWM_1:PWMUDB:status_2\ | \PWM_1:PWMUDB:status_2\/q | \PWM_1:PWMUDB:genblk8:stsreg\/status_2 | 2.303
statusicell1 | U(1,1) | 1 | \PWM_1:PWMUDB:genblk8:stsreg\ |  | SETUP | 1.570
Clock |  |  |  |  | Skew | 0.000
\PWM_1:PWMUDB:runmode_enable\/q | \PWM_1:PWMUDB:genblk8:stsreg\/status_2 | 85.346 MHz | 11.717 | 999988.283 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
macrocell2 | U(1,1) | 1 | \PWM_1:PWMUDB:runmode_enable\ | \PWM_1:PWMUDB:runmode_enable\/clock_0 | \PWM_1:PWMUDB:runmode_enable\/q | 1.250
Route |  | 1 | \PWM_1:PWMUDB:runmode_enable\ | \PWM_1:PWMUDB:runmode_enable\/q | \PWM_1:PWMUDB:status_2\/main_0 | 3.244
macrocell1 | U(1,1) | 1 | \PWM_1:PWMUDB:status_2\ | \PWM_1:PWMUDB:status_2\/main_0 | \PWM_1:PWMUDB:status_2\/q | 3.350
Route |  | 1 | \PWM_1:PWMUDB:status_2\ | \PWM_1:PWMUDB:status_2\/q | \PWM_1:PWMUDB:genblk8:stsreg\/status_2 | 2.303
statusicell1 | U(1,1) | 1 | \PWM_1:PWMUDB:genblk8:stsreg\ |  | SETUP | 1.570
Clock |  |  |  |  | Skew | 0.000
\PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb | \PWM_1:PWMUDB:prevCompare1\/main_0 | 87.009 MHz | 11.493 | 999988.507 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
datapathcell1 | U(1,1) | 1 | \PWM_1:PWMUDB:sP8:pwmdp:u0\ | \PWM_1:PWMUDB:sP8:pwmdp:u0\/clock | \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb | 5.680
Route |  | 1 | \PWM_1:PWMUDB:cmp1_less\ | \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb | \PWM_1:PWMUDB:prevCompare1\/main_0 | 2.303
macrocell3 | U(1,1) | 1 | \PWM_1:PWMUDB:prevCompare1\ |  | SETUP | 3.510
Clock |  |  |  |  | Skew | 0.000
\PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb | \PWM_1:PWMUDB:status_0\/main_1 | 87.009 MHz | 11.493 | 999988.507 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
datapathcell1 | U(1,1) | 1 | \PWM_1:PWMUDB:sP8:pwmdp:u0\ | \PWM_1:PWMUDB:sP8:pwmdp:u0\/clock | \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb | 5.680
Route |  | 1 | \PWM_1:PWMUDB:cmp1_less\ | \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb | \PWM_1:PWMUDB:status_0\/main_1 | 2.303
macrocell4 | U(1,1) | 1 | \PWM_1:PWMUDB:status_0\ |  | SETUP | 3.510
Clock |  |  |  |  | Skew | 0.000
\PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb | Net_85/main_1 | 87.009 MHz | 11.493 | 999988.507 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
datapathcell1 | U(1,1) | 1 | \PWM_1:PWMUDB:sP8:pwmdp:u0\ | \PWM_1:PWMUDB:sP8:pwmdp:u0\/clock | \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb | 5.680
Route |  | 1 | \PWM_1:PWMUDB:cmp1_less\ | \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb | Net_85/main_1 | 2.303
macrocell5 | U(1,1) | 1 | Net_85 |  | SETUP | 3.510
Clock |  |  |  |  | Skew | 0.000
\PWM_1:PWMUDB:genblk1:ctrlreg\/control_7 | \PWM_1:PWMUDB:runmode_enable\/main_0 | 119.019 MHz | 8.402 | 999991.598 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
controlcell1 | U(1,1) | 1 | \PWM_1:PWMUDB:genblk1:ctrlreg\ | \PWM_1:PWMUDB:genblk1:ctrlreg\/clock | \PWM_1:PWMUDB:genblk1:ctrlreg\/control_7 | 2.580
Route |  | 1 | \PWM_1:PWMUDB:control_7\ | \PWM_1:PWMUDB:genblk1:ctrlreg\/control_7 | \PWM_1:PWMUDB:runmode_enable\/main_0 | 2.312
macrocell2 | U(1,1) | 1 | \PWM_1:PWMUDB:runmode_enable\ |  | SETUP | 3.510
Clock |  |  |  |  | Skew | 0.000
\PWM_1:PWMUDB:runmode_enable\/q | Net_85/main_0 | 124.440 MHz | 8.036 | 999991.964 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
macrocell2 | U(1,1) | 1 | \PWM_1:PWMUDB:runmode_enable\ | \PWM_1:PWMUDB:runmode_enable\/clock_0 | \PWM_1:PWMUDB:runmode_enable\/q | 1.250
Route |  | 1 | \PWM_1:PWMUDB:runmode_enable\ | \PWM_1:PWMUDB:runmode_enable\/q | Net_85/main_0 | 3.276
macrocell5 | U(1,1) | 1 | Net_85 |  | SETUP | 3.510
Clock |  |  |  |  | Skew | 0.000
\PWM_1:PWMUDB:prevCompare1\/q | \PWM_1:PWMUDB:status_0\/main_0 | 141.764 MHz | 7.054 | 999992.946 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
macrocell3 | U(1,1) | 1 | \PWM_1:PWMUDB:prevCompare1\ | \PWM_1:PWMUDB:prevCompare1\/clock_0 | \PWM_1:PWMUDB:prevCompare1\/q | 1.250
Route |  | 1 | \PWM_1:PWMUDB:prevCompare1\ | \PWM_1:PWMUDB:prevCompare1\/q | \PWM_1:PWMUDB:status_0\/main_0 | 2.294
macrocell4 | U(1,1) | 1 | \PWM_1:PWMUDB:status_0\ |  | SETUP | 3.510
Clock |  |  |  |  | Skew | 0.000

+ Hold Subsection
+ Source Clock : Clock_1 : Positive edge
+ Destination Clock : Clock_1 : Positive edge

Source | Destination | Slack (ns) | Violation
--- | --- | --- | ---
\PWM_1:PWMUDB:status_0\/q | \PWM_1:PWMUDB:genblk8:stsreg\/status_0 | 1.561 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
macrocell4 | U(1,1) | 1 | \PWM_1:PWMUDB:status_0\ | \PWM_1:PWMUDB:status_0\/clock_0 | \PWM_1:PWMUDB:status_0\/q | 1.250
Route |  | 1 | \PWM_1:PWMUDB:status_0\ | \PWM_1:PWMUDB:status_0\/q | \PWM_1:PWMUDB:genblk8:stsreg\/status_0 | 2.311
statusicell1 | U(1,1) | 1 | \PWM_1:PWMUDB:genblk8:stsreg\ |  | HOLD | -2.000
Clock |  |  |  |  | Skew | 0.000
\PWM_1:PWMUDB:prevCompare1\/q | \PWM_1:PWMUDB:status_0\/main_0 | 3.544 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
macrocell3 | U(1,1) | 1 | \PWM_1:PWMUDB:prevCompare1\ | \PWM_1:PWMUDB:prevCompare1\/clock_0 | \PWM_1:PWMUDB:prevCompare1\/q | 1.250
Route |  | 1 | \PWM_1:PWMUDB:prevCompare1\ | \PWM_1:PWMUDB:prevCompare1\/q | \PWM_1:PWMUDB:status_0\/main_0 | 2.294
macrocell4 | U(1,1) | 1 | \PWM_1:PWMUDB:status_0\ |  | HOLD | 0.000
Clock |  |  |  |  | Skew | 0.000
\PWM_1:PWMUDB:genblk1:ctrlreg\/control_7 | \PWM_1:PWMUDB:runmode_enable\/main_0 | 4.352 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
controlcell1 | U(1,1) | 1 | \PWM_1:PWMUDB:genblk1:ctrlreg\ | \PWM_1:PWMUDB:genblk1:ctrlreg\/clock | \PWM_1:PWMUDB:genblk1:ctrlreg\/control_7 | 2.040
Route |  | 1 | \PWM_1:PWMUDB:control_7\ | \PWM_1:PWMUDB:genblk1:ctrlreg\/control_7 | \PWM_1:PWMUDB:runmode_enable\/main_0 | 2.312
macrocell2 | U(1,1) | 1 | \PWM_1:PWMUDB:runmode_enable\ |  | HOLD | 0.000
Clock |  |  |  |  | Skew | 0.000
\PWM_1:PWMUDB:runmode_enable\/q | Net_85/main_0 | 4.526 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
macrocell2 | U(1,1) | 1 | \PWM_1:PWMUDB:runmode_enable\ | \PWM_1:PWMUDB:runmode_enable\/clock_0 | \PWM_1:PWMUDB:runmode_enable\/q | 1.250
Route |  | 1 | \PWM_1:PWMUDB:runmode_enable\ | \PWM_1:PWMUDB:runmode_enable\/q | Net_85/main_0 | 3.276
macrocell5 | U(1,1) | 1 | Net_85 |  | HOLD | 0.000
Clock |  |  |  |  | Skew | 0.000
\PWM_1:PWMUDB:runmode_enable\/q | \PWM_1:PWMUDB:sP8:pwmdp:u0\/cs_addr_1 | 4.533 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
macrocell2 | U(1,1) | 1 | \PWM_1:PWMUDB:runmode_enable\ | \PWM_1:PWMUDB:runmode_enable\/clock_0 | \PWM_1:PWMUDB:runmode_enable\/q | 1.250
Route |  | 1 | \PWM_1:PWMUDB:runmode_enable\ | \PWM_1:PWMUDB:runmode_enable\/q | \PWM_1:PWMUDB:sP8:pwmdp:u0\/cs_addr_1 | 3.283
datapathcell1 | U(1,1) | 1 | \PWM_1:PWMUDB:sP8:pwmdp:u0\ |  | HOLD | 0.000
Clock |  |  |  |  | Skew | 0.000
\PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb | \PWM_1:PWMUDB:prevCompare1\/main_0 | 5.433 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
datapathcell1 | U(1,1) | 1 | \PWM_1:PWMUDB:sP8:pwmdp:u0\ | \PWM_1:PWMUDB:sP8:pwmdp:u0\/clock | \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb | 3.130
Route |  | 1 | \PWM_1:PWMUDB:cmp1_less\ | \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb | \PWM_1:PWMUDB:prevCompare1\/main_0 | 2.303
macrocell3 | U(1,1) | 1 | \PWM_1:PWMUDB:prevCompare1\ |  | HOLD | 0.000
Clock |  |  |  |  | Skew | 0.000
\PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb | \PWM_1:PWMUDB:status_0\/main_1 | 5.433 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
datapathcell1 | U(1,1) | 1 | \PWM_1:PWMUDB:sP8:pwmdp:u0\ | \PWM_1:PWMUDB:sP8:pwmdp:u0\/clock | \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb | 3.130
Route |  | 1 | \PWM_1:PWMUDB:cmp1_less\ | \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb | \PWM_1:PWMUDB:status_0\/main_1 | 2.303
macrocell4 | U(1,1) | 1 | \PWM_1:PWMUDB:status_0\ |  | HOLD | 0.000
Clock |  |  |  |  | Skew | 0.000
\PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb | Net_85/main_1 | 5.433 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
datapathcell1 | U(1,1) | 1 | \PWM_1:PWMUDB:sP8:pwmdp:u0\ | \PWM_1:PWMUDB:sP8:pwmdp:u0\/clock | \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb | 3.130
Route |  | 1 | \PWM_1:PWMUDB:cmp1_less\ | \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb | Net_85/main_1 | 2.303
macrocell5 | U(1,1) | 1 | Net_85 |  | HOLD | 0.000
Clock |  |  |  |  | Skew | 0.000
\PWM_1:PWMUDB:sP8:pwmdp:u0\/z0_comb | \PWM_1:PWMUDB:sP8:pwmdp:u0\/cs_addr_2 | 5.846 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
datapathcell1 | U(1,1) | 1 | \PWM_1:PWMUDB:sP8:pwmdp:u0\ | \PWM_1:PWMUDB:sP8:pwmdp:u0\/clock | \PWM_1:PWMUDB:sP8:pwmdp:u0\/z0_comb | 3.270
datapathcell1 | U(1,1) | 1 | \PWM_1:PWMUDB:sP8:pwmdp:u0\ | \PWM_1:PWMUDB:sP8:pwmdp:u0\/z0_comb | \PWM_1:PWMUDB:sP8:pwmdp:u0\/cs_addr_2 | 2.576
datapathcell1 | U(1,1) | 1 | \PWM_1:PWMUDB:sP8:pwmdp:u0\ |  | HOLD | 0.000
Clock |  |  |  |  | Skew | 0.000
\PWM_1:PWMUDB:runmode_enable\/q | \PWM_1:PWMUDB:genblk8:stsreg\/status_2 | 8.147 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
macrocell2 | U(1,1) | 1 | \PWM_1:PWMUDB:runmode_enable\ | \PWM_1:PWMUDB:runmode_enable\/clock_0 | \PWM_1:PWMUDB:runmode_enable\/q | 1.250
Route |  | 1 | \PWM_1:PWMUDB:runmode_enable\ | \PWM_1:PWMUDB:runmode_enable\/q | \PWM_1:PWMUDB:status_2\/main_0 | 3.244
macrocell1 | U(1,1) | 1 | \PWM_1:PWMUDB:status_2\ | \PWM_1:PWMUDB:status_2\/main_0 | \PWM_1:PWMUDB:status_2\/q | 3.350
Route |  | 1 | \PWM_1:PWMUDB:status_2\ | \PWM_1:PWMUDB:status_2\/q | \PWM_1:PWMUDB:genblk8:stsreg\/status_2 | 2.303
statusicell1 | U(1,1) | 1 | \PWM_1:PWMUDB:genblk8:stsreg\ |  | HOLD | -2.000
Clock |  |  |  |  | Skew | 0.000

+ Clock To Output Section
+ Clock_1

Source | Destination | Delay (ns)
--- | --- | ---
Net_85/q | LED(0)_PAD | 22.960
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
macrocell5 | U(1,1) | 1 | Net_85 | Net_85/clock_0 | Net_85/q | 1.250
Route |  | 1 | Net_85 | Net_85/q | LED(0)/pin_input | 5.880
iocell1 | P0[2] | 1 | LED(0) | LED(0)/pin_input | LED(0)/pad_out | 15.830
Route |  | 1 | LED(0)_PAD | LED(0)/pad_out | LED(0)_PAD | 0.000
Clock |  |  |  |  | Clock path delay | 0.000